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ADF7242 Datasheet(PDF) 67 Page - Analog Devices |
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ADF7242 Datasheet(HTML) 67 Page - Analog Devices |
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67 / 108 page  ADF7242 Rev. 0 | Page 67 of 108 CONFIGURATION VALUES COMMON TO IEEE 802.15.4 AND GFSK/FSK MODES If it is desired to use RF Port 1 rather than RF Port 2 (see the RF Port Configurations/Antenna Diversity section), the value specific to the desired operating mode given in Table 36 should be written to the relevant register field. Table 36. Settings Required to Select Between LNA Port 1 and LNA Port 2 Address Register Field Value 0x39B [6:4] rxfe_cfg, lna_sel 0x0: LNA1 0x1: LNA2 CONFIGURATION VALUES FOR GFSK/FSK PACKET AND SPORT MODES If it is desired to use either GFSK/FSK packet or SPORT mode, the host MCU should write the configuration values shown in Table 37 to the given register locations. These are common to all GFSK/FSK packet and SPORT modes. Depending on the desired data rate, the relevant values from Table 38 should also be written. Table 37. Settings Common to All GFSK/FSK Configurations Address Register Name Value 0x335 synt 0x28 0x3B2 agc_cfg1 0x34 0x3B4 agc_max 0x80 0x3B6 agc_cfg2 0x37 0x3B7 agc_cfg3 0x2A 0x3B8 agc_cfg4 0x1D 0x3BA agc_cfg6 0x24 0x3BC agc_cfg7 0x7B 0x3BF ocl_cfg0 0x00 0x3C4 ocl_cfg1 0x07 0x3D2 ocl_bw0 0x1A 0x3D3 ocl_bw1 0x19 0x3D4 ocl_bw2 0x1E 0x3D5 ocl_bw3 0x1E 0x3D6 ocl_bw4 0x1E 0x3D7 ocl_bws 0x00 0x3E0 ocl_bw13 0xF0 0x3F3 preamble_num_validate 0x01 Table 38. Data Rate-Specific GFSK/FSK Settings Address Register or Field Name 50 kbps FSK 62.5 kbps FSK 100 kbps FSK 125 kbps FSK 250 kbps GFSK 500 kbps GFSK 1 Mbps GFSK 2 Mbps GFSK 0x1021 fsk_preamble 0x04 (6 bytes) 0x04 (6 bytes) 0x05 (7 bytes) 0x05 (7 bytes) 0x05 (7 bytes) 0x05 (7 bytes) 0x07 (9 bytes) 0x09 (11 bytes) 0x304 tx_fd 0x03 0x06 0x03 0x06 0x0D 0x19 0x19 0x32 0x305 dm_cfg0 0x37 0x37 0x6B 0x37 0x19 0x0D 0x0D 0x06 0x306 tx_m 0x00 0x00 0x00 0x00 0x02 0x03 0x03 0x03 0x30E dr0 0x01 0x02 0x03 0x04 0x09 0x13 0x27 0x4E 0x30F dr1 0xF4 0x71 0xE8 0xE2 0xC4 0x88 0x10 0x20 0x389 Iirf_cfg 0x17 0x17 0x17 0x17 0x12 0x0A 0x05 0x05 0x38B dm_cfg1 0x08 0x08 0x0D 0x11 0x20 0x3D 0x6E 0xAA 0x39B [3:0] rxfe_cfg, rxbb_bw_ana 0x6 0x6 0x6 0x6 0x6 0x6 0x6 0xD 1 This register should be written to in GFSK/FSK packet mode only. The preamble length transmitted that is given in this table is correct for the values of Register preamble_num_validate given in Table 37 and Register sync_config given in Table 40, where sync_word0 is padded with one byte of preamble. Refer to the Transmitter in GFSK/FSK Mode section for details. |
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