ADF7242 datasheet(72/108 Pages) AD

72 / 108 page

ADF7242

Rev. 0 | Page 72 of 108

SERIAL PERIPHERAL INTERFACE (SPI)

GENERAL CHARACTERISTICS

The ADF7242 is equipped with a 4-wire SPI interface, using the

SCLK, MISO, MOSI, and CS pins. The ADF7242 always acts as

a slave to the host MCU.

shows an example connec-

tion diagram between the host MCU and the ADF7242. The

diagram also shows the direction of the signal flow for each pin.

The SPI interface is active and the MISO output enabled only

while the

Figure 101

CS input is low. The interface uses a word length of

eight bits, which is compatible with the SPI hardware of most

microprocessors. The data transfer through the SPI interface

occurs with the most significant bit of address and data first.

Refer to

for the SPI interface timing diagram. The

MOSI input is sampled at the rising edge of SCLK. As

commands or data are shifted in from the MOSI input at the

SCLK rising edge, the status word or data is shifted out at the

MISO pin synchronous with the SCLK clock falling edge. If

Figure 3

is brought low, the most significant bit of the status word

appears on the MISO output without the need for a rising clock

edge on the SCLK input.

SCLK

MOSI

MISO

IRQ2_TRFS_GP2

DR_GP0

DT_GP1

TRCLK_CKO_GP3

IRQ1_GP4

PF1

SCLK

MOSI

MISO

RFS

RSCLK

TSCLK

GPI

ADF7242

VBAT

ADSP-21xx

BLACKFIN

DSP

Figure 101. SPI Interface Connection

COMMAND ACCESS

The ADF7242 is controlled through commands. Command

words are single-byte instructions that control the state

transitions of the radio controller and access to the registers and

packet RAM. The complete list of valid commands is given in

Table 45. Commands with the RC prefix are handled by the

radio controller, whereas memory access commands, which

have the SPI prefix are handled by an independent controller.

Thus, SPI commands can be issued independent of the state of

the radio controller.

A command is initiated by bringing CS low and shifting in the

command word over the SPI as shown in

Figure 102

All commands are executed after CS goes high again or at the

next positive edge of the SCLK input. The latter condition

occurs in the case of a memory access command. In this case,

the command is executed on the positive SCLK clock edge

corresponding to the most significant bit of the first parameter

word. The CS input must be brought high again after a

command has been shifted into the ADF7242 to enable the

recognition of successive command words. This is because a

single command can be issued only during a CS low period

(with the exception of a double NOP command).

RC OR SPI

COMMAND

STATUS

MOSI

MISO

Figure 102. Command Write

The execution of certain commands by the radio controller may

take several instruction cycles, during which the radio control-

ler unit is busy. Prior to issuing a radio controller command, it

is, therefore, necessary to read the status word to determine if

the ADF7242 is ready to accept a new radio controller command.

This is best accomplished by shifting in SPI_NOP commands,

which cause status words to be shifted out. The RC_READY

variable is used to indicate when the radio controller is ready to

accept a new RC command, whereas the SPI_READY variable

indicates when the memory can be accessed. To take the burden

of repeatedly polling the status word off the host MCU for

complex commands such as RC_RX, RX_TX, and RC_PHY_RDY,

the IRQ handler can be configured to generate an RC_READY

interrupt. See the Interrupt Controller section for details.

Otherwise, the user can program timeout periods according to

the command execution times provided under the state transi-

tion timing given in Table 10 and Table 11.

STATUS WORD

The status word of the ADF7242 is automatically returned over

the MISO each time a byte is transferred over the MOSI. The

meaning of the various status word bit fields is illustrated in

Table 46. The RC_STATUS field reflects the current state of the

radio controller. By definition, RC_STATUS reflects the state of

a completed state transition. During the state transition,

RC_STATUS maintains the value of the state from which the

state transition was invoked.

ADF7242 Datasheet(PDF) 72 Page - Analog Devices

ADF7242 Datasheet(HTML) 72 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL