10 _____________________________________________________________________________________

20-Bit, Single-Channel, Ultra-Low-Power, Delta-

Sigma ADCs with Programmable Gain and GPIO

2.048MHz oscillator. The 2.4576MHz oscillator provides

maximum 60Hz rejection, and the 2.048MHz oscillator

provides maximum 50Hz rejection. See Figures 1 and

2. For optimal simultaneous 50Hz and 60Hz rejection,

apply a 2.25275MHz external clock at CLK.

Reference

The devices provide differential inputs REFP and REFN

for an external reference voltage. Connect the external

reference directly across the REFP and REFN to obtain

the differential reference voltage. The common-mode

The devices accept reference inputs in buffered or

unbuffered mode. The value of the REFBUF bit in the

CTRL1 register determines whether the reference buffer

is enabled or disabled. See Table 12.

Buffers

The devices include reference and signal input buffers

capable of reducing the average input current from

2.1FA/V on the reference inputs and from 1.4FA/V on

the analog inputs to a constant 30nA current on the

reference inputs and 20nA current on the analog inputs.

The reference and signal input buffers can be selected

individually by programming the CTRL1 register bits

REFBUF and SIGBUF. When enabled, the reference and

input signal buffers require an additional 20FA from the

AVDD supply pin.

Power-On Reset (POR)

The devices utilize power-on reset (POR) supply-mon-

itoring circuitry on both the digital supply (DVDD) and

the analog supply (AVDD). The POR circuitry ensures

proper device default conditions after either a digital or

analog power sequencing event. The digital POR trig-

ger threshold is approximately 1.2V and has 100mV of

hysteresis. The analog POR trigger threshold is approxi-

mately 1.25V and has 100mV of hysteresis. Both POR

circuits have lowpass filters that prevent high-frequency

supply glitches from triggering the POR.

Calibration

The devices provide two sets of calibration registers

which offer the user several options for calibrating

their system. The calibration register value defaults

are all zero, which require a user to either perform

a calibration or program the register through the SPI

interface to use them. The on-chip calibration reg-

isters are enabled or disabled by programming the

NOSYSG, NOSYSO, NOSCG, and NOSCO bits in the

CTRL3 register. The default values for these calibra-

tion control bits are 1, which disables the use of the

internal calibration registers.

The devices power up with the internal calibration regis-

ters disabled, and therefore a full-scale input produces

a result of 60% of the full-scale digital range. To use the

full-scale digital range a calibration must be performed.

The first level of calibration is the self-calibration where

the part performs the required connections to zero and

full-scale internally. This level of calibration is typically

sufficient for 1FV of offset accuracy and 2ppm of full-

scale accuracy. The self-calibration routine does not

include the source resistance effects from the signal

source driving the input pins, which can change the off-

set and gain of the system.

A second level of calibration is available where the user

can calibrate a system zero scale and system full scale

by presenting a zero-scale signal or a full-scale signal

to the input pins and initiating a system zero scale or

system gain calibration command.

A third level of calibration allows for the user to write to

the internal calibration registers through the SPI interface

to achieve any digital offset or scaling the user requires

with the following restrictions. The range of digital offset

tion is from 0.5 to 1.5. The resolution of offset correction

is 0.5 LSB.

The calibration operations are controlled with the CAL1

and CAL0 bits in the command byte. The user requests

a self-calibration by setting the CAL1 bit to 0 and CAL0

bit to 1. A self-calibration requires 200ms to complete,

and both the SCOC and SCGC registers contain the

values that correct the chip output for zero scale and full

scale. The user requests a system zero-scale calibration

by setting the CAL1 bit to 1 and the CAL0 bit to 0 and

presents a system zero-level signal to the input pins. The

SOC register contains the values that correct the chip

zero scale. The system zero calibration requires 100ms

to complete, and the SOC register contains values that

correct the chip zero scale. The user requests a system

full-scale calibration by setting the CAL1 bit to 1 and the

CAL0 bit to 1 and presents a system full-scale signal

level to the input pins. The system full-scale calibration

requires 100ms to complete, and the SGC register con-

tains values that correct for the chip full-scale value. See

Tables 3a and 3b for an example of a self-calibration

sequence and a system calibration sequence.