16 _____________________________________________________________________________________

20-Bit, Single-Channel, Ultra-Low-Power, Delta-

Sigma ADCs with Programmable Gain and GPIO

Table 7. Operating Mode (MODE Bit)

Table 8. Command Byte (MODE = 0, LINEF = 0)

Table 9. Register Selection (MODE = 1)

COMMAND

START

MODE

CAL1

CAL0

IMPD

RATE2

RATE1

RATE0

Self-calibration cycle

1

0

0

1

0

0

0

0

System offset calibration cycle

1

0

1

0

0

0

0

0

System gain calibration

1

0

1

1

0

0

0

0

Immediate power-down

1

0

0

0

1

0

0

0

Convert 1sps

1

0

0

0

0

0

0

0

Convert 2.5sps

1

0

0

0

0

0

0

1

Convert 5sps

1

0

0

0

0

0

1

0

Convert 10sps

1

0

0

0

0

0

1

1

Convert 15sps

1

0

0

0

0

1

0

0

Convert 30sps

1

0

0

0

0

1

0

1

Convert 60sps

1

0

0

0

0

1

1

0

Convert 120sps

1

0

0

0

0

1

1

1

RS3

RS2

RS1

RS0

REGISTER ACCESS

POWER-ON RESET STATUS

REGISTER SIZE (BITS)

0

0

0

0

STAT1

0x00

8

0

0

0

1

CTRL1

0x02

8

0

0

1

0

CTRL2

0x0F

8

0

0

1

1

CTRL3

0x1E

8

0

1

0

0

DATA

0x000000

24

0

1

0

1

SOC

0x000000

24

0

1

1

0

SGC

0x000000

24

0

1

1

1

SCOC

0x000000

24

1

0

0

0

SCGC

0x000000

24

MODE BIT SETTING

OPERATING MODE

0

The command byte initiates a conversion or an immediate power-down. See Tables 5 and 8.

1

The device interprets the command byte as a register access byte, which is decoded as per

Tables 6 and 9.