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20-Bit, Single-Channel, Ultra-Low-Power, Delta-

Sigma ADCs with Programmable Gain and GPIO

Table 10. Register Address Map

*These DGAIN_ bits set the digital gain for the MAX11206. These bits are don’t-care bits for the MAX11207.

REGISTER

NAME

R/W

ADDRESS

SEL (RS[3:0])

B7

B6

B5

B4

B3

B2

B1

B0

STAT1

R

0x0

SYSOR

RATE2

RATE1

RATE0

OR

UR

MSTAT

RDY

CTRL1

R/W

0x1

LINEF

U/B

EXTCLK

REFBUF

SIGBUF

FORMAT

SCYCLE RESERVED

CTRL2

R/W

0x2

DIR4

DIR3

DIR2

DIR1

DIO4

DIO3

DIO2

DIO1

CTRL3

R/W

0x3

DGAIN2*

DGAIN1*

DGAIN0*

NOSYSG

NOSYSO

NOSCG

NOSCO RESERVED

DATA

R

0x4

D[19:16]

D[15:8]

D[7:0]

SOC

R/W

0x5

B[23:16]

B[15:8]

B[7:0]

SGC

R/W

0x6

B[23:16]

B[15:8]

B[7:0]

SCOC

R/W

0x7

B[23:16]

B[15:8]

B[7:0]

SCGC

R/W

0x8

B[23:16]

B[15:8]

B[7:0]