24 _____________________________________________________________________________________

20-Bit, Single-Channel, Ultra-Low-Power, Delta-

Sigma ADCs with Programmable Gain and GPIO

Table 20. SCGC Register (Read/Write)

SCGC: Self-Calibration Gain Register

The self-calibration gain register is a 24-bit read/write register. The data written/read to/from this register is clocked

in/out MSB first. This register holds the self-calibration gain calibration value. The format is always in two’s complement

binary format. A write to the self-calibration register is allowed. The written value remains valid until it is either rewritten

or until an on-demand self-calibration operation is performed, which overwrites the user-supplied value. Any attempt

to write to this register during an active calibration operation is ignored.

The self-calibration gain value is used to scale the self-calibration offset corrected conversion result before the system

offset and gain calibration values have been applied, provided the NOSCG bit in the CTRL3 register is set to 0. The

self-calibration gain value scales the self-calibration offset corrected conversion result by up to 2x or can correct a gain

error of approximately -50%. The gain is corrected to within 2 LSB.

Table 21. Data Rates for All Combinations of RATE[2:0] (LINEF = 0)

Table 22. Data Rates for All Combinations of RATE[2:0] (LINEF = 1)

BIT

B23

B22

B21

B20

B19

B18

B17

B16

DEFAULT

0

0

0

0

0

0

0

0

BIT

B15

B14

B13

B12

B11

B10

B9

B8

DEFAULT

0

0

0

0

0

0

0

0

BIT

B7

B6

B5

B4

B3

B2

B1

B0

DEFAULT

0

0

0

0

0

0

0

0

RATE[2:0]

SINGLE-CYCLE DATA RATE (sps)

CONTINUOUS DATA RATE (sps)

000

1

—

001

2.5

—

010

5

—

011

10

—

100

15

60

101

30

120

110

60

240

111

120

480

RATE[2:0]

SINGLE-CYCLE DATA RATE (sps)

CONTINUOUS DATA RATE (sps)

000

0.833

—

001

2.08

—

010

4.17

—

011

8.33

—

100

12.5

50

101

25

100

110

50

200

111

100

400