18 _____________________________________________________________________________________

20-Bit, Single-Channel, Ultra-Low-Power, Delta-

Sigma ADCs with Programmable Gain and GPIO

STAT1: Status Register

SYSOR: The system gain overrange bit, when set to 1, indicates that a system gain calibration was over range. The

SCGC calibration coefficient is maximum value of 1.9999999. This bit, when set to 1, indicates that the full-scale value

out of the converter is likely not available.

RATE[2:0]: The data rate bits indicate the conversion rate that corresponds to the result in the DATA register or the

rate that was used for calibration coefficient calculation. If the previous conversions were done at a different rate, the

RATE[2:0] bits indicate a rate different than the rate of the conversion in progress.

OR: The overrange bit, OR, is set to 1 to indicate the conversion result has exceeded the maximum value of the

converter and that the result has been clipped or limited to the maximum value. The OR bit is set to 0 to indicate the

conversion result is within the full-scale range of the device.

UR: The underrange bit, UR, is set to 1 to indicate the conversion result has exceeded the minimum value of the

converter and that the result has been clipped or limited to the minimum value. The UR bit is set to 0 to indicate the

conversion result is within the full-scale range of the device.

MSTAT: The measurement status bit, MSTAT is set to 1 when a signal measurement is in progress. When MSTAT = 1,

a conversion, self-calibration, or system calibration is in progress and indicates that the modulator is busy. When the

modulator is not converting, the MSTAT bit is set to 0.

RDY: The RDY ready bit is set to 1 to indicate that a conversion result is available. Reading the DATA register resets the

RDY bit to 0 only after another conversion has been initiated. If the DATA has not been read before another conversion

is initiated, the RDY bit remains 1; if the DATA is read before another conversion is initiated, the RDY bit resets to 0. If

the DATA for the previous conversion is read during a following conversion, the RDY bit is reset immediately after the

DATA read operation has completed.

Table 11. STAT1 Register (Read Only)

BIT

B7

B6

B5

B4

B3

B2

B1

B0

BIT NAME

SYSOR

RATE2

RATE1

RATE0

OR

UR

MSTAT

RDY

DEFAULT

0

0

0

0

0

0

0

0