41210 datasheet(1/52 Pages) INTEL

Part #	41210

Description	Intel 41210 Serial to Parallel PCI Bridge

PDF	52 Pages

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Manufacturer	INTEL [Intel Corporation]

Direct Link	http://www.intel.com

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1 / 52 page

Order Number: 278875-005US

May 2005

Intel® 41210 Serial to Parallel PCI Bridge

Datasheet

Product Features

■

PCI Express Specification, Revision 1.0a

■

Support for single x8, single x4 or single x1

PCI Express operation.

■

64-bit addressing support

■

32-bit CRC (cyclic redundancy checking)

covering all transmitted data packets.

■

16-bit CRC on all link message

information.

■

Raw bit-rate on the data pins of 2.5 Gbit/s,

resulting in a raw bandwidth per pin of

250 MB/s.

■

Maximum realized bandwidth on PCI

Express interface is 2 GB/s (in x8 mode) in

each direction simultaneously, for an

aggregate of 4 GB/s.

■

PCI Local Bus Specification, Revision 2.3.

■

PCI-to-PCI Bridge Specification,

Revision 1.1.

■

PCI-X Addendum to the PCI Local Bus

Specification, Revision 1.0b

■

64-bit 66 MHz, 3.3 V, NOT 5 V tolerant.

■

On Die Termination (ODT) with 8.3KOhm

pull-up to 3.3V for PCI signals.

■

Six external REQ/GNT Pairs for internal

arbiter on segment A and B respectively.

■

Programmable bus parking on either the

last agent or always on the 41210 Bridge

■

2-level programmable round-robin internal

arbiter with Multi-Transaction Timer

(MTT)

■

External PCI clock-feed support for

asynchronous primary and secondary

domain operation.

■

64-bit addressing for upstream and

downstream transactions

■

Downstream LOCK# support.

■

No upstream LOCK# support.

■

PCI fast Back-to-Back capable as target.

■

Up to four active and four pending

upstream memory read transactions

■

Up to two downstream delayed (memory

read, I/O read/write and configuration read/

write) transaction.

■

Tunable inbound read prefetch algorithm

for PCI MRM/MRL commands

■

Device hiding support for secondary PCI

devices.

■

Secondary bus Private Memory support via

Opaque memory region

■

Local initialization via SMBus

■

Secondary side initialization via Type 0

configuration cycles.

■

Full peer-to-peer read/write capability

between the two secondary PCI segments.

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