41210 datasheet(32/52 Pages) INTEL

32 / 52 page

41210 Bridge — Datasheet

1. See the timing measurement conditions in Section 3.5, “Timing Specifications” on page 28.

2. Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X

Electrical and Mechanical Addendum, Revision 2.0a. Maximum times are measured with the test point and

load circuit shown in PCI-X Electrical and Mechanical Addendum, Revision 2.0a.

3. See the timing measurement conditions in Section 3.5, “Timing Specifications” on page 28 and the PCI-X

Electrical and Mechanical Addendum, Revision 2.0a.

4. RST# is asserted and deasserted asynchronously with respect to CLK.

5. For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total

current delivered through the component pin is less than or equal to the leakage current specification

6. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at

the same time.

7. Maximum value is also limited by delay to the first transaction (Trhfa). The PCI-X initialization pattern control

signals after the rising edge of RSTIN# must be deasserted no later than two clocks before the first

PxFRAME# and must be floated no later than one clock before PxFRAME# is asserted.

8. Device must meet this specification independent of how many outputs switch simultaneously.

Ton

Float to Active Delay

1, 6, 8

Toff

Active to Float Delay

1, 6, 8

Tsu

Input Setup Time to CLK

1.2

1.7

3, 7

Input Hold Time from CLK

0.5

Trst

Reset Active Time after power

stable

Trst-clk

Reset Active Time after CLK stable

100

µs4

Trst-off

Reset Active to output float delay

Trrsu

PxREQ64# to RSTIN# setup time

Trrh

RSTIN# to PxREQ64# hold Time

Trhfa

RSTIN# high to first configuration

access

226

clocks

Trhff

RSTIN# high to first PxFRAME#

Assertion

clocks

Tpvrh

Power valid to RSTIN# high

100

Tprsu

PCI-X initialization pattern to

RSTIN# setup time

clocks

Tprh

RSTIN# to PCI-X initialization

pattern hold time

Trlcx

Delay from RSTIN# low to CLK

frequency change

Table 25.

PCI-X 3.3V Signal Timing Parameters (Sheet 2 of 2)

41210 Datasheet(PDF) 32 Page - Intel Corporation

41210 Datasheet(HTML) 32 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL