41210 datasheet(35/52 Pages) INTEL

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Datasheet — 41210 Bridge

3.5.4

41210 Bridge Clock Timings

1. Period, jitter, offset and skew measured on rising edge @ 1.5V for 3.3V clocks.

Table 27.

41210 Bridge Clock Timings

Symbol

Parameter

Min

Max

Units

Notes

CLK100

Tperiod

Average Period

10.0

10.2

Trise

Rise time across 600 mV

300

600

7,8

Tfall

Fall time across 600 mV

300

600

7,8

—

Rise/Fall Matching

20%

7,9

—

Cross point at 1 V

0.51

0.76

Tccjitter

Cycle to Cycle jitter

200

—Duty Cycle

—

Maximum voltage allowed at input

1.45

—

Minimum voltage allowed at input

-200

—

Rising edge ringback

0.85

—

Falling edge ring back

0.35

CLK133

Tperiod

Average Period

7.5

7.65

Trise

Rise time across 600 mV

300

600

7,8

Tfall

Fall time across 600 mV

300

600

7,8

—

Rise/Fall Matching

20%

7,9

—

Cross point at 1V

0.51

0.76

Tccjitter

Cycle to Cycle jitter

125

—Duty Cycle

—

Maximum voltage allowed at input

1.45

—

Minimum voltage allowed at input

-200

—

Rising edge ringback

0.85

—

Falling edge ring back

0.35

CLK33

Tperiod

CLK period

30.0

N/A

1,2

Thigh

CLK high time

12.0

N/A

Tlow

CLK low time

12.0

N/A

—

Rising edge rate

1.0

4.0

V/ns

—

Falling edge rate

1.0

4.0

V/ns

Trise

CLK rise time

0.5

2.0

Tfall

CLK fall time

0.5

2.0

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