IR3502

Page 9 of 39

July 28, 2009

SYSTEM THEORY OF OPERATION

System Description

The system consists of one control IC and a scalable array of phase converters, each requiring one phase IC. The

control IC communicates with the phase ICs using three digital buses, i.e., CLOCK, PHSIN, PHSOUT and three

analog buses, i.e., VDAC, EA, IIN. The digital buses are responsible for switching frequency determination and

accurate phase timing control without any external component. The analog buses are used for PWM control and

current sharing among interleaved phases. The control IC incorporates all the system functions, i.e., VID, CLOCK

signals, error amplifier, fault protections, current monitor, etc. The Phase IC implements the functions required by

each phase of the converter, i.e., the gate drivers, PWM comparator and latch, over-voltage protection, Phase

disable circuit, current sensing and sharing, etc.

PWM

COMPARATOR

RDRP1

OFF

VSETPT

CLKIN

RCS

CCS

ISHARE

PHSIN

DACIN

VCC

CSIN+

GATEL

EAIN

GATEH

CBST

VCCH

CSIN-

SW

PGND

VCCL

RTHRM

VID6

PHSOUT

VID6

RCOMP

OFF

CLK

D

Q

PHSIN

PSI

CCOMP

OFF

VID6

RFB

VID6

+

-

CLKIN

CDRP

RCS

CCS

RDRP

3K

GND

VOUT

DACIN

VCC

VDAC

VO

LGND

ISHARE

PHSIN

VOSNS-

VOSNS+

GATEL

EAIN

GATEH

IIN

VDRP

VIN

FB

EAOUT

CLKOUT

CSIN-

CSIN+

IROSC

VID6

VDAC

REMOTE SENSE

AMPLIFIER

VCCH

CBST

CLK

D

Q

Q

U246

DFFRH

VCCL

GATE DRIVE

VOLTAGE

PHSOUT

PWM

COMPARATOR

VID6

VID6

PSI

VID6

CLK

D

Q

+

-

3K

VID6

CLK

D

Q

Q

U248

DFFRH

VID6

+

VID6

+

-

+

BODY

BRAKING

COMPARATOR

RAMP

DISCHARGE

CLAMP

ENABLE

CURRENT

SENSE

AMPLIFIER

RVSETPT

PWM LATCH

SHARE ADJUST

ERROR AMPLIFIER

RESET

DOMINANT

1

2

PHASE IC

PGND

VID6

PSI

-

+

SW

VID6

+

+

Thermal

Compensation

ENABLE

RAMP

DISCHARGE

CLAMP

VDRP

AMP

VDAC

BODY

BRAKING

COMPARATOR

VN

IVSETPT

CLOCK GENERATOR

PWM LATCH

CURRENT

SENSE

AMPLIFIER

IMON

ERROR

AMPLIFIER

SHARE ADJUST

ERROR AMPLIFIER

RESET

DOMINANT

RFB1

COUT

CONTROL IC

CFB

1

2

PSI

PHASE IC

PHSOUT

OFF

VID6

Figure 3 System Block Diagram

PWM Control Method

The PWM block diagram of the XPhase3

with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the control IC is

used for the voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The

PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage.

The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace

voltage drop related to changes in load current.

Frequency and Phase Timing Control

The oscillator is located in the control IC and the system clock frequency is programmable from 250kHz to 9MHZ by

an external resistor. The control IC system clock signal CLKOUT is connected to CLKIN of all the phase ICs. The

phase timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output PHSOUT is