34704 datasheet(7/54 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

34704

PIN CONNECTIONS

A/B

SW2D

Input/Output

REG2 Buck Stage

switching node

The inductor is connected between this pin and the SW2U pin.

A/B

VOUT2

Output

REG2 regulated output

voltage pin

Connect this pin to the load and to the output filter as close to

the pin as possible.

A/B

SW2U

Input/Output

REG2 Boost Stage

switching node

The inductor is connected between this pin and the SW2D pin.

A/B

SW5U

Input/Output

REG5 Boost Stage

switching node

The inductor is connected between this pin and the SW5D pin.

A/B

VOUT5

Output

REG5 regulated output

voltage pin

Connect this pin to the load and to the output filter as close to

the pin as possible.

A/B

SW5D

Input/Output

REG5 Buck Stage

switching node

The inductor is connected between this pin and the SW5U pin.

A/B

PVIN5

Power

REG5 power supply input

voltage

This is the connection to the drain of the high side switch FET.

Input decoupling /filtering is required for proper REG5 operation.

Use a 10uf decoupling capacitor for better performance

A/B

BT5D

Passive

REG5 Buck Stage

bootstrap capacitor input

Connect a 1.0

μF capacitor between this pin and SW5D pin to

enhance the gate of the Switch Power MOSFET.

A/B

FB5

Input

REG5 voltage feedback

input for voltage

regulation/programming

Connect the feedback resistor divider to this pin.

A/B

COMP5

Passive

REG5 compensation

network connection

REG5 compensation network connection.

Exposed

Pad

A/B

PGND

Ground

Power Ground

Connection for all of the

regulators except REG7

Power Ground Connection for all of the regulators except

REG7. This pad is provided to enhance thermal performance.

Notes

If regulator 1 is not used, leave pin 23 Unconnected, All other components should be used to provide VG to the system

If regulators 5, 6, 7 and 8 are not used, connect the corresponding pins as follows: FB node: tied to GND, BT node: Not connected, VOUT

node: Tied to GND, SW node: Tied to GND, DRV node: Tied to GND (REG7 only), COMP pin: Not connected, PVIN Pin: Not connected.

REG 2,3 and 4 should always be populated.

Table 2. 34704 Pin Definitions (continued)

A functional description of each pin can be found in the Functional Pin Description section beginning on page 17.

Pin Number Device Pin Name Pin Function

Formal Name

Definition

34704 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc

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