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ADC1413D Datasheet(PDF) 3 Page - NXP Semiconductors |
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ADC1413D Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 43 page ![]() ADC1413D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 February 2011 3 of 43 NXP Semiconductors ADC1413D series Dual 14-bit ADC; serial JESD204A interface 5. Block diagram Fig 1. Block diagram ERROR CORRECTION AND DIGITAL PROCESSING CLOCK INPUT STAGE AND DUTY CYCLE CONTROL ADC A CORE 14-BIT PIPELINED T/H INPUT STAGE ERROR CORRECTION AND DIGITAL PROCESSING CLOCK INPUT STAGE AND DUTY CYCLE CONTROL SYSTEM REFERENCE AND POWER MANAGEMENT ADC B CORE 14-BIT PIPELINED T/H INPUT STAGE ADC1413D DLL PLL SERIALIZER A SPI OUTPUT BUFFER A SERIALIZER B OUTPUT BUFFER B 8-bit 8-bit INAP INAM CLKP CLKM INBP SCRAMBLER RESET INBM 8-bit 8-bit 10-bit 10-bit SWING_n SWING_n SYNCP SCLK CFG (0 to 3) SDIO CS SYNCN CMLNB CMLPB CMLNA CMLPA OTR D13 to D0 D13 to D0 OTR 005aaa067 REFAT REFAB REFBB REFBT VCMA VREF SENSE VCMB |
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