ADC1413D datasheet(14/43 Pages) NXP

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ADC1413D_SER

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Product data sheet

Rev. 5 — 9 February 2011

14 of 43

NXP Semiconductors

ADC1413D series

Dual 14-bit ADC; serial JESD204A interface

11. Application information

11.1 Analog inputs

11.1.1 Input stage description

The analog input of the ADC1413D supports a differential or a single-ended input drive.

Optimal performance is achieved using differential inputs with the common-mode input

voltage (VI(cm)) on pins INxP and INxM set to 0.5VDDA.

The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)

via a programmable internal reference (see Section 11.2 and Table 21).

Figure 6 shows the equivalent circuit of the sample-and-hold input stage, including

ElectroStatic Discharge (ESD) protection and circuit and package parasitics.

The sample phase occurs when the internal clock (derived from the clock signal on pin

CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the

clock signal goes LOW, the stage enters the hold phase and the voltage information is

transmitted to the ADC core.

Fig 6.

Input sampling circuit

005aaa069

INAP

INBP

package

ESD

parasitics

switch

Ron = 15 Ω

4 pF

switch

Ron = 15 Ω

INAM

INBM

1, 14

2, 13

internal

clock

internal

clock

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