 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADC1413D Datasheet(PDF) 11 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
ADC1413D Datasheet(HTML) 11 Page - NXP Semiconductors |
|
|
11 / 43 page  xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx [1] Typical values measured at VDDA =3V, VDDD =1.8 V, Tamb =25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA =3V, VDDD = 1.8 V; VI (INAP, INBP) VI (INAM, INBM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs; unless otherwise specified. 10.2 Clock and digital output timing [1] Typical values measured at VDDA =3V, VDDD =1.8 V, Tamb =25 C. Minimum and maximum values are across the full temperature range Tamb = 40 C to +85 C at VDDA =3V, VDDD = 1.8 V; VI (INAP, INBP) VI (INAM, INBM) = 1 dBFS; internal reference mode; 100 W differential applied to serial outputs; unless otherwise specified. IMD intermodulation distortion fi = 3 MHz - 89 - - 89 - - 88 - - 89 - dBc fi = 30 MHz -88- -88- -88- - 88 - dBc fi = 70 MHz -87- -87- -86- - 86 - dBc fi = 170 MHz - 84 - - 85 - - 83 - - 84 - dBc ct(ch) channel crosstalk fi = 70 MHz - 100 - - 100 - - 100 - - 100 - dBc Table 6. Dynamic characteristics[1] …continued Symbol Parameter Conditions ADC1413D065 ADC1413D080 ADC1413D105 ADC1413D125 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Table 7. Clock and digital output characteristics[1] Symbol Parameter Conditions ADC1413D065 ADC1413D080 ADC1413D105 ADC1413D125 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Clock timing input: pins CLKP and CLKM fclk clock frequency 40 - 65 60 - 80 75 - 105 100 - 125 Msps tlat(data) data latency time clock cycles 307 - 850 250 - 283 190 - 226 160 - 170 ns clk clock duty cycle DCS_EN = logic 1 30 50 70 30 50 70 30 50 70 30 50 70 % td(s) sampling delay time - 0.8 - - 0.8 - - 0.8 - - 0.8 - ns twake wake-up time -76- -76- -76- -76- s |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
