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ADC1413D Datasheet(PDF) 32 Page - NXP Semiconductors |
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ADC1413D Datasheet(HTML) 32 Page - NXP Semiconductors |
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32 / 43 page ![]() ADC1413D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 February 2011 32 of 43 NXP Semiconductors ADC1413D series Dual 14-bit ADC; serial JESD204A interface Table 30. Ser_Control1 (address 0805h) Default values are highlighted. Bit Symbol Access Value Description 7 - - 0 not used 6 TRISTATE_CFG_PINS R/W 1 pins CFG3 to CFG0 are set to high-impedance. Switch to 0 automatically after start-up or reset. 5 SYNC_POL R/W defines the sync signal polarity: 0 synchronization signal is active LOW 1 synchronization signal is active HIGH 4 SYNC_SINGLE_ENDED R/W defines the input mode of the sync signal: 0 synchronization input mode is set in Differential mode 1 synchronization input mode is set in Single-ended mode 3 - - 1 not used 2 REV_SCR - LSBs are swapped with MSBs at the scrambler input: 0 disable 1 enable 1 REV_ENCODER - LSBs are swapped with MSBs at the 8-bit/10-bit encoder input: 0 disable 1 enable 0 REV_SERIAL - LSBs are swapped with MSBs at the lane input: 0 disable 1enable Table 31. Ser_Control2 (address 0806h) Default values are highlighted. Bit Symbol Access Value Description 7 to 2 - - 000000 not used 1 SWAP_LANE_0_1 R/W swaps the outputs of the JESD204A unit. (output buffer A is connected to Lane 1, output buffer B is connected to Lane 0): 0 disable 1enable 0 SWAP_ADC_A_B R/W swaps the inputs of the JESD204A unit. (ADC A output is connected to input B, ADC B is connected to input A): 0 disable 1enable Table 32. Ser_Analog_Ctrl (address 0808h) Default values are highlighted. Bit Symbol Access Value Description 7 to 3 - - 00000 not used 2 to 0 SWING_SEL[2:0] R/W 011 defines the swing output for the lane pads |
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