ADF7241 datasheet(39/72 Pages) AD

39 / 72 page

ADF7241

Rev. 0 | Page 39 of 72

If a busy channel is detected during the CCA phase, the radio

controller performs the next delay/CCA cycle until the maxi-

mum number of CCA retries specified has been reached. If the

maximum number of allowed CCA retries has been reached,

the operation is aborted, and the device transitions to the

PHY_RDY state.

If the CCA is successful, the radio controller changes the device

state from the CCA state to the TX state and transmits the

frame stored in TX_BUFFER. The minimum turnaround time

from RX to TX is 106 μs. If neither the acknowledge request bit

in the transmitted frame nor the csma_ca_turnaround bit are set,

the device returns to the PHY_RDY state immediately upon

completion of the frame transmission. Otherwise, it enters the

RX state and waits for up to 864 μs for an acknowledgment. If an

acknowledgment is not received within this time and the

maximum number of frame retries has not been reached, the

ADF7241 remains inside the frame transmit retry loop and

starts the next CSMA/CA cycle. Otherwise, it exits to the PHY_

RDY state. The procedure exits with a csma_ca_complete interrupt.

RECEIVER RADIO BLOCKS

Baseband Filter

Baseband filtering on the ADF7241 is accomplished by a cascade of

analog and digital filters. These are configured for optimum

performance assuming a crystal frequency tolerance of ±40 ppm.

Offset Correction Loop (OCL)

The ADF7241 is equipped with a fast and autonomous offset

correction loop (OCL), which cancels both static and dynamic

time-varying offset voltages present in the zero-IF receiver path.

The OCL operates continuously and is not constrained by the

formatting, timing, or synchronization of the data being

received. The scheme is suitable for frequency hopping spread-

spectrum (FHSS) communication systems.

Automatic Gain Control (AGC) and Receive Signal

Strength Indicator (RSSI)

The ADF7241 AGC circuit features fast overload recovery using

dynamic bandwidth adjustments for fast preamble acquisition

and optimum utilization of the dynamic range of the receiver path.

The radio controller automatically enables the AGC after an

offset correction phase, which is carried out when the trans-

ceiver enters the RX state.

The RSSI readback value is continuously updated while the

ADF7241 is in the RX state. The result is provided in Register rrb,

Field rssi_readback (0x30C[7:0]) in decibels relative to 1 mW

(dBm) using signed twos complement notation. The RSSI

averaging window is synchronized with the start of the active

RX phase at the end of the MAC delay following an RC_RX

command.

The RSSI averaging period is 128 μs, or eight symbol periods, in

compliance with the IEEE 802.15.4-2006 standard. If the ADF7241

is operating in the IEEE 802.15.4-2006 packet mode, the RSSI of

received frames is measured and stored together with the frame

in RX_BUFFER. The RSSI is measured in a window with a length

of eight symbols immediately following the detected SFD. The

result is then stored in place of the first byte of the FCS of the

received frame in RX_BUFFER. It is also possible to compen-

sate for systematic errors of the measured RSSI value and/or

production tolerances by adjusting the RSSI readback value by

an offset value that can be programmed in Register agc_cfg5,

Field rssi_offs (0x3B9[4:2]). The adjustment resolution is in

1 dB steps.

ADF7241 Datasheet(PDF) 39 Page - Analog Devices

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