ADF7241 datasheet(33/72 Pages) AD

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ADF7241

Rev. 0 | Page 33 of 72

RECEIVER

RECEIVE OPERATION

The two primary receiver operating modes are

•

IEEE 802.15.4-2006 packet manager mode

•

IEEE 802.15.4-2006 SPORT mode

The desired operating mode is selected with Register rc_cfg,

Field rc_mode. The SPORT modes are explained in more detail

in the SPORT Interface section.

The output of the post demodulator filter is fed into a bank of

correlators, which compare the incoming data sequences to the

expected IEEE 802.15.4-2006 sequences. The receiver block

operates in three primary states.

•

Preamble qualification

•

Symbol timing recovery

•

Data symbol reception

During preamble qualification, the correlators check for the pres-

ence of preamble. When preamble is qualified, the device enters

symbol timing recovery mode. The device symbol timing is

achieved once a valid SFD is detected. The ADF7241 supports

programmable SFDs. Refer to the Programmable SFD section

for further details.

The received symbols are then passed to the packet manager in

packet mode or the SPORT interface in SPORT mode. In SPORT

mode, four serial clocks are output on Pin TRCLK_CKO_GP3,

and four data bits are shifted out on Pin DR_GP0 for each received

symbol. Refer to the SPORT Interface section for further details.

If in packet mode, when the packet manager determines the end

of a packet, the ADF7241 automatically transitions to PHY_RDY

or TX or remains in RX, depending on the setting in Register

buffercfg, Field rx_buffer_mode (see Receiver Configuration in

Packet Mode section). If in SPORT mode, the part remains in

RX until the user issues a command to change to another state.

Programmable SFD

An alternative to the standard IEEE 802.15.4-2006 SFD byte can

optionally be selected by the user. The default setting of Register

sfd_15_4, Field sfd_symbol_1 and Field sfd_symbol_2 (0x3F4[7:0])

is the standard IEEE 802.15.4-2006 SFD. If the user programs

this register with an alternative value, this is used as the SFD in

receive and transmit. The requirements are as follows:

•

The value must not be a repeated symbol (for example, not

0x11 or 0x22).

•

The value must not be similar to the preamble symbol (that

is, not Symbol 0x0 or Symbol 0x8).

Receiver Configuration in Packet Mode

Packet management support is selected when Register rc_cfg,

Field rc_mode = 0 (0x13E[7:0]). RX_BUFFER is overwritten

when the ADF7241 enters the RX state following an RC_RX

command and an SFD is detected. The SFD is stripped off the

incoming frame, and all data following and including the frame

length (PHR) is written to RX_BUFFER.

If Register pkt_cfg, Field auto_fcs_off = 1, the FCS of the incoming

frame is stored in RX_BUFFER. When the entire frame has been

received, an rx_pkt_rcvd interrupt is asserted irrespective of the

correctness of the FCS. If auto_fcs_off = 0, the radio controller

calculates the FCS of the incoming frame according to the FCS

polynomial defined in the IEEE 802.15.4-2006 standard (see

Equation 1), and compares the result against the FCS of the

incoming frame. An rx_pkt_rcvd interrupt is asserted only if

both FCS fields match. The FCS is not written to RX_BUFFER

but is replaced with the measured RSSI and signal quality

indicator (SQI ) values of the received frame (see Figure 41).

)

(

(1)

The behavior of the radio controller following the reception

of a frame can be configured with Register buffercfg, Field rx_

buffer_mode (0x107[1:0]). With the default setting rx_buffer_

mode = 0, the part reverts automatically to PHY_RDY when an

rx_pkt_rcvd interrupt condition occurs. This mode prevents

RX_BUFFER from being overwritten by the next frame before

the host MCU can read it from the ADF7241. This is because a

new frame is always written to RX_BUFFER starting from the

address stored in Register rxpb, Field rx_pkt_base (0x315[7:0]).

Note that reception of the next frame is inhibited until the MAC

delay following an RC_RX command has elapsed.

If Register buffercfg, Field rx_buffer_mode = 1 (0x107[1:0]),

the part remains in the RX state, and the reception of the next

packet is enabled one MAC delay period after the frame has

been written to RX_BUFFER. Depending on the network setup,

this mode can cause an unnoticed violation of RX_BUFFER

integrity if a frame arrives prior to the MCU having read the

frame from RX_BUFFER.

If Register buffercfg, Field rx_buffer_mode = 2 (0x107[1:0]),

the reception of frames is disabled. This mode is useful for RSSI

measurements and CCA, if the contents of RX_BUFFER are to

be preserved.

RECEIVER CALIBRATION

The receive path is calibrated each time an RC_RX command is

issued. Figure 42 outlines the synthesizer and receive path

calibration sequence and timing. The calibration step VCO_cal is

omitted by setting Register vco_cal_cfg, Field skip_vco_cal = 15

(0x36F[3:0]), which is an option if the value of ch_freq[23:0]

remains unchanged during transitions between the PHY_RDY,

RX, and TX states. The synthesizer settling phase is always

required because the PLL bandwidth is optimized differently for

RX and TX operation. The static offset correction phase

(OCL_stat) and dynamic offset correction phase (OCL_dyn) are

also mandatory.

ADF7241 Datasheet(PDF) 33 Page - Analog Devices

ADF7241 Datasheet(HTML) 33 Page - Analog Devices

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