ADF7241 datasheet(25/72 Pages) AD

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ADF7241

Rev. 0 | Page 25 of 72

Sleep States

SLEEP_BBRAM_XTO

The sleep state is entered with the RC_SLEEP command. The

sleep state can be configured to operate in three different

modes, which are listed in Table 17.

This mode enables the 32 kHz crystal oscillator and retains

certain configuration registers in the BBRAM during the sleep

state. To enable SLEEP_BBRAM_XTO mode, set Register

tmr_cfg1, Field sleep_config = 5. A wake-up interrupt can be

set using, for example, Register irq1_en0, Field wakeup = 1.

Refer to the Wake-Up Controller (WUC) section for details on

how to configure the ADF7241 WUC.

Table 17. ADF7241 Sleep Modes

Sleep Mode

Active

Circuits

Functionality

SLEEP_BBRAM

BBRAM

Packet RAM and modem

configuration register (MCR)

contents are not maintained.

BBRAM retains the IEEE

802.15.4-2006 node

addresses1.

SLEEP_BBRAM_RCO

This mode enables the 32 kHz RC oscillator and retains certain

configuration registers in the BBRAM during the sleep state.

This mode can be used when lower timer accuracy is acceptable

by the communication system. It is enabled by setting Register

tmr_cfg1, Field sleep_config = 11. A wake-up interrupt can be

set using, for example, Register irq1_en0, Field wakeup = 1.

Refer to the Wake-Up Controller (WUC) section for details on

how to configure the ADF7241 WUC.

SLEEP_BBRAM_XTO

BBRAM and

32 kHz

crystal

oscillator

32 kHz crystal oscillator is

enabled, with data retention

in the BBRAM.

SLEEP_BBRAM_RCO

BBRAM and

32 kHz RC

Oscillator

32 kHz RC oscillator is

enabled, with data retention

in the BBRAM.

Wake-Up from the Sleep State

The host MCU can bring CS low at any time to wake the

ADF7241 from the sleep state. After bringing CS low, it must

wait until the MISO output (SPI_READY flag) goes high prior

to accessing the SPI port. This delay reflects the start-up time of

the ADF7241. When the MISO output is high, the voltage

regulator of the digital section and the crystal oscillator have

stabilized. Unless the chip is in the sleep state, the MISO pin

always goes high immediately after bringing CS low. The sleep

state can also be exited by a timeout event with the WUC

configured. Refer to the

section

for details on how to configure the ADF7241 WUC.

Wake-Up Controller (WUC)

1 Refer to the Receiver Configuration in Packet Mode section for further

details.

SLEEP MODES

The sleep modes are configurable with the wake-up configura-

tion registers, tmr_cfg0 and tmr_cfg1. The contents of Register

tmr_cfg0 and Register tmr_cfg1 are reset in the sleep state.

SLEEP_BBRAM

This mode is suitable for applications where the MCU is equipped

with its own wake-up timer. SLEEP_BBRAM mode is enabled

by setting Register tmr_cfg1, Field sleep_config = 1.

t15

RC_RESET

(0xC8)

IDLE

SLEEP

APPLY

VDD_BAT

SPI COMMAND

TO ADF7241

DEVICE STATE

Figure 31. Cold Start Sequence from Application of the Battery

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