Electronic Components Datasheet Search
  English  ▼

X  

33480 Datasheet(PDF) 26 Page - Freescale Semiconductor, Inc

Part # 33480
Description  Smart Front Corner Light
PDF  39 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33480 Datasheet(HTML) 26 Page - Freescale Semiconductor, Inc

Back Button 33480 Datasheet HTML 22Page - Freescale Semiconductor, Inc 33480 Datasheet HTML 23Page - Freescale Semiconductor, Inc 33480 Datasheet HTML 24Page - Freescale Semiconductor, Inc 33480 Datasheet HTML 25Page - Freescale Semiconductor, Inc 33480 Datasheet HTML 26Page - Freescale Semiconductor, Inc 33480 Datasheet HTML 27Page - Freescale Semiconductor, Inc 33480 Datasheet HTML 28Page - Freescale Semiconductor, Inc 33480 Datasheet HTML 29Page - Freescale Semiconductor, Inc 33480 Datasheet HTML 30Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 26 / 39 page
background image
Analog Integrated Circuit Device Data
26
Freescale Semiconductor
33480
PROTECTION AND DIAGNOSIS FEATURES
The current recopy feature for OUT1:5 is disabled during
high overcurrent shutdown phase (t2) and is only enabled
during low overcurrent shutdown threshold. The current
recopy output delivers current only during ON time of the
output switch without overshoot (aperiodic settling).
The current recopy is not active in Fail Mode.
TEMPERATURE PREWARNING
The 33480 provides a temperature prewarning reported
via SPI (OTW bit) in Normal Mode. The information is
latched. To delatch, a read SPI command is needed. In case
of Power on Reset, the fault will be reset.
EXTERNAL TERMINAL STATUS
The 33480 provides the status of the FLASHER, IGN, and
CLOCK terminals via SPI in real time and in Normal Mode.
FAILURE HANDLING STRATEGY
A highly sophisticated failure handling strategy enables
light functionality even in case of failures inside the
component or the light module. Components are protected
against:
• Reverse Polarity
• Loss of Supply Lines
• Fatal Mistreatment of Logic I/O Terminals
REVERSE POLARITY PROTECTION ON VBAT
In case of permanently reverse polarity operation, the
output transistors are turned ON (Rsd) to prevent thermal
overload and no protections are available.
External diode on Vcc is necessary in order to not destroy
the 33480 in case of reverse polarity.
In case of negative transients on the VBAT line (per
ISO 7637), the VCC line is still operating, while the VBAT line
is negative. Therefore, the device is protected against latch-
up.
LOSS OF SUPPLY LINES
The 33480 is protected against loss of any supply line. The
detection of the supply line failure is provided inside the
device itself.
LOSS OF VBAT
During undervoltage of VBAT (VBATPOR<VBAT<VBATUV)
and with active device (wake=1), the outputs [1-5] are
switched off and the external MOSFET remains in the
previous state. No current path from Vbat to Vcc. The
external MOSFET (OUT6) can be controlled by SPI if Vcc
remains and is above to VCCUV. The fault is reported to UVF
bit (OD13). To delatch the fault, the undervoltage condition
should be removed and:
• The bit D7 must be rewritten to logic [1] in Normal Mode.
Application of OCHI window depends on toggling or not
toggling D7 bit. When the fault is delatched, the 33480
returns in the configuration it was just before the failure.
• If the device was in Fail mode, the fault will be delatched
by the Autorestart feature periodically.
In case of VBAT<VBATPOR (Power OFF state), all latched
faults are reset if VCC < VBAT. In case of VBAT is missing, all
outputs (out[1:6]) are OFF and no current is conducted from
Vcc to VBAT.
LOSS OF VCC (DIGITAL LOGIC SUPPLY LINE)
During loss of VCC (VCC < VCCUV) and with wake=1, the
33480 is switched automatically into Fail mode (no deglich
time). The external SMART MOSFET is OFF. All SPI
registers are reset and must be reprogrammed when Vcc
goes above VCCUV.
LOSS OF GROUND (GND)
During loss of ground, the 33480 cannot operate the loads
(the outputs (1:5) are switched OFF) but is not destroyed by
the operating condition. Current limit resistors in the digital
input lines protect the digital supply against excessive current
(1kohm typical). The state of the external smart power switch
controlled by FETout is not guaranteed and the state of
external smart MOS is defined with external termination
resistor.
FATAL MISTREATMENT OF LOGIC I/O
TERMINALS
The digital I/Os are protected against fatal mistreatment
by signal plausibility check according to Table 6.
In case of LIMP input is set to logic [1] for a delay longer
than 10ms typical, the 33480 is switched into Fail mode. In
case of (PWM) Clock failure, no PWM feature is provided and
Table 6. Logic I/O Plausibility Check
Input/Output
Signal Check Strategy
LIMP
Debounce for 10 ms
(PWM) CLOCK
Frequency range
(bandpass filter)
SPI (MOSI, SCLK, CS)
WD, D10 bit internal toggle



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com