33480 datasheet(12/39 Pages) FREESCALE

12 / 39 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33480

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.5 V

≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 18 V, -40°C ≤ TA ≤ 125°C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUTS TIMING (OUT1 to OUT5)

Current Sense rising and falling Settling Time on resistive load only (Maximum

Value, 5%)

tR5 / tF5

–

µs

Current Sense rising and falling Settling Time on resistive load only (Maximum

Value, 1%)

tR1 / tR5

–

TBD

µs

Driver Output Positive Slew Rate (30% to 70% @ VBAT = 14 V)

IOUT = 2.8 A for OUT1 and OUT5

IOUT = 5.5 A for OUT2, OUT3, and OUT4

SRR

0.2

0.4

0.8

µs

Driver Output Negative Slew Rate (70% to 30% @ VBAT = 14 V)

IOUT = 2.8 A for OUT1 and OUT5

IOUT = 5.5 A for OUT2, OUT3, and OUT4

SRF

0.2

0.4

0.8

µs

Driver Output Matching Slew Rate (SRR /SRF) (70% to 30% @ VBAT = 14 V

@25°C)

IOUT = 2.8 A for OUT1 and OUT5

IOUT = 5.5 A for OUT2, OUT3, and OUT4

∆SR

0.8

1.0

1.2

Driver Output Turn-ON Delay (SPI ON Command [No PWM, CS Positive Edge]

to Output = 50% VBAT @ VBAT = 14 V) (

IOUT = 2.8 A for OUT1 and OUT5

IOUT = 5.5 A for OUT2, OUT3, and OUT4

tDLYON

160 (TBC)

µs

Driver Output Turn-OFF Delay (SPI OFF command [CS Positive Edge] to

Output = 50% VBAT @ VBAT = 14 V) (see Figure4, p14)

IOUT = 2.8 A for OUT1 and OUT5

IOUT = 5.5 A for OUT2, OUT3, and OUT4

tDLYOFF

160 (TBC)

µs

Driver Output Matching Time (

tDLY(ON) - tDLY(OFF)) @ Output = 50% VBAT with

VBAT = 14 V, fPWM = 240 Hz, δPWM = 50%, @25°C

IOUT = 2.8 A for OUT1 and OUT5

IOUT = 5.5 A for OUT2, OUT3, and OUT4

∆tRF

-25

µs

PWM MODULE

PWM Frequency Range

fPWM

60.0

–

240.0

Clock Input Frequency Range

fCLK

7.68

–

30.72

kHz

Output PWM Duty Cycle maximum range for 11V<Vbat<18V (35)

PWM_MAX

4.0

–

96.0

Output PWM Duty Cycle linear range for 11V<Vbat<18V (36)

PWM_LIN

6.2 (TBC)

–

96.0 (TBC)

WATCHDOG TIMING

Watchdog Timeout (SPI Failure)

tWDTO

100

I/O PLAUSIBILITY CHECK TIMING

Fault Shutdown Delay Time (from Overtemperature or OCHI1 or OCHI2 or

OCLO Fault Detection to Output = 50%VBAT without round shaping feature

for turn off)

tSD

–

µs

33480 Datasheet(PDF) 12 Page - Freescale Semiconductor, Inc

33480 Datasheet(HTML) 12 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Datasheet Download

Link URL