33480 datasheet(30/39 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33480

FUNCTIONAL DESCRIPTION

PROTECTION AND DIAGNOSIS FEATURES

ADDRESS 01110—CONTROL EXTERNAL SWITCH

Same description as OUT1.

ADDRESS 01111 —TEST MODE

This register is reserved for test and is not available with

SPI during normal operation.

SERIAL OUTPUT COMMUNICATION (DEVICE

STATUS RETURN

DATA)

When the CS terminal is pulled low, the output register is

loaded. Meanwhile, the data is clocked out MSB first as the

new message data is clocked into the SI terminal. The first

16 bits of data clocking out of the SO, and following a CS

transition, is dependant upon the previously written SPI word

(SOA1 and SOA0 defined in the last SPI initialization word).

Any bits clocked out of the SO terminal after the first 16 will

be representative of the initial message bits clocked into the

SI terminal since the CS terminal first transitioned to a

logic [0]. This feature is useful for daisy chaining devices.

A valid message length is determined following a CS

transition of logic [0] to logic [1]. If the message length is

valid, the data is latched into the appropriate registers. A valid

message length is a multiple of 16 bits. At this time, the SO

terminal is tri-stated and the fault status register is now able

to accept new fault status information.

The output status register correctly reflects the status of

the Initialization-selected register data at the time that the CS

is pulled to a logic [0] during SPI communication and/or for

the period of time since the last valid SPI communication,

with the following exceptions:

• The previous SPI communication was determined to be

invalid. In this case, the status will be reported as

though the invalid SPI communication never occurred.

• Battery transients below 6.0 V, resulting in an under-

voltage shutdown of the outputs, may result in incorrect

data loaded into the status register.

SERIAL OUTPUT BIT ASSIGNMENT

The contents of bits OD15:OD0 depend on bits D1:D0

from the most recent initialization command SOA[1:0] (refer

to Table 8, page 28), as explained in the paragraphs that

follow.

The register bits are reset by a read operation and also if

the fault is removed.

Table 11 summarizes the SO register content. Bit OD10

reflects Normal mode (NM).

Table 11. Serial Output Bit Map Description

Status/

Mode

SI Data

SO Data

OD15 OD14 OD13 OD12 OD11 OD10 OD9

OD8

OD7

OD6

OD5

OD4

OD3

OD2

OD1

OD0

Output

Status

UVF OTW OTS

OL5

OVL5

OL4

OVL4

OL3

OVL3

OL2

OVL2

OL1

OVL1

Overload

Status

UVF OTW OTS

OC5

OTS5

OC4

OTS4

OC3

OTS3

OC2

OTS2

OC1

OTS1

Device

Status

UVF OTW OTS

FLASHER

IGN

CLOCK

fail

Test

Mode

UVF OTW OTS

Reset

33480 Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

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