33781 datasheet(22/44 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33781

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

SPI0 COMMUNICATIONS

All SPI0 transactions are either 16 or 32-bits long. They

start with a command byte and can be followed by 1 or 3

bytes of data. The start of an SPI transaction is signaled by

CS0

being asserted low. The first bit sent (bit 7) of the first

byte signals a read or write (write = 1) of data. The last seven

bits (bits 6–0) of the command set a pointer to the desired

registers, and 32-bit commands to access both control

registers, and to queue up transfers over the DBUS.

Figure 13 is a diagram of 16-bit transfers and Figure 14 is a

diagram of 32-bit transfers. In these multi-byte transfers, as

long as CS0 is asserted low, each additional byte sent over

the SPI will be a read/write of data to the sequential next

33781 utilizes, transmit, and receive addressable FIFOs

for sending commands and responses over the DBUS. There

are separate command and response registers, and a

transmit queue is used to allow up to 4 bus commands to be

scheduled for each bus. The transmit queue schedules

commands as a circular buffer, accessing the appropriate

command register for the command and data to be sent as

the bus becomes available. Data received in response to the

commands is queued up for sequential response back to the

MCU during the next set of SPI commands. If an SPI0

attempts to write to a transmit register that is not empty the

new command will be ignored.

Figure 14 shows an example of a write operation. During

the first byte of the SPI transaction, the first MOSI bit is 1

(write), and the last seven are the address of the register to

be accessed. During this command byte, MISO returns

dummy bits set to all zeros. During the next SPI transactions,

MOSI updates the data in the register pointed to in the

previous byte with new data, while reading back the old data

via MISO.

During an SPI0 transaction the 33781 checks for SPI

framing errors. A framing error is defined as any number of

clocks received that is not either 16 or 32. If that occurs, all

bits sent by the SPI master are discarded and no registers

are update.

Figure 13. SPI016-Bit Burst Transfer Example.

Figure 14. SPI0 32-Bit Burst Transfer Example

The bit definitions for SPI0 depend on the type of SPI

transfer, and if the transfer will be to/from the addressable

FIFOs, whether the DBUS for that channel is set for Long

Words or Enhanced Short words.

Figure 13 shows the bit encoding for 16-bit SPI0 burst

transfers. In this transfer the first byte contains the address of

the control register to be written to or read from, and the

second byte is the data to be written. The SPI0 response is

the data from that register, latched at the falling edge of CS0.

If the address pointed to by the first byte is not a control

WRITE COMMAND

POINT TO REGISTER

00000000

DATA TO

DATA FROM

CS0

SCLK

MOSI

MISO

WRITE COMMAND

POINT TO D0R0H

CS0

SCLK

MOSI

MISO

DATA TO D0R0H

DATA TO D0R0L

XXXXXXXX

00000000

DATA FROM D0R0H

DATA FROM D0R0L

DATA FROM D0R0STAT

33781 Datasheet(PDF) 22 Page - Freescale Semiconductor, Inc

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