33781 datasheet(24/44 Pages) FREESCALE

24 / 44 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33781

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Figure 17. SPI0 Communications, 32-Bit Burst Transfer Enhanced Short Word DBUS Bit Definitions

SPI1 COMMUNICATIONS

All SPI1 transactions are read only, are 16-bits in length,

and are asynchronous to SPI0. There is no MOSI pin or

function associated with SPI1, since there are no commands

sent. Figure 18 shows the signals associated with an SPI1

transfer, and Figure 19 contains the order of bits sent for

each SPI1 transaction.

SPI1 transfers start with the 1st SCLK1 transition after

CS1 asserts and ends once CS1 negates. The start of an SPI

transaction is signaled by CS1 being asserted low. If the SPI1

logic sees more than 16 SCLK1 pulses while CS1 is

asserted, zeros are returned for all additional bits (bits

beyond bit 15). If a SPI1 transaction contains less than 16-

bits (too few SCLK cycles), the data that was in process of

being sent during the transaction is discarded and not saved

for retry.

There are eight registers which can be read by SPI1 in a

cyclic fashion. Four of these registers are associated with bus

channel 2, and four are associated with bus channel 3. Data

is deposited into these registers under the following

conditions:

When the bus channel 2 is set for enhanced 10-bit short

words, the SPI1 state machine monitors outgoing bus

addresses and commands on the channel. If the command

sent is $2 (Request AN0), the address portion of the

command is saved. The response received on the next

command is stored into one of the four 16-bit register pointed

to by the channel 2 cyclic buffer write pointer, along with the

address that generated that response (saved from the

previous transaction) with the bits “01”, completing the 16 bit

write. These last two bits indicate that the transaction

occurred on channel 2. The data bits will only be written if the

status bits for that bus transaction all indicate no errors. If a

status error is indicated, the address and channel indicator

bits are stored as described, but the data bits are all set to

zeros. If there was a bus driver shutdown during the

transaction, no buffer write will occur. Further transactions

are written to the next cyclic buffer register in the same way,

overwriting data if necessary.

This same sequence occurs for channel three

transactions, except that the channel indicator bits are “10”,

and writes occur to a separate set of four 16-bit cyclic

registers.

If the channel has been put into loop mode, the same

sequence is used except the buffer write occurs only if the

data is all ones or all zeros, and the saved address from the

previous transaction is the complement of the data. The

channel indicator bits are written the same as if the channel

were in normal mode. The buffer pointer always advances,

even if the buffer is not written, so that it is synchronous with

the SPI0 RX buffer pointer.

The channel buffers are not cleared, in the case of a

channel abort.

Reads from this register by the SPI1 master are also

accomplished in a cyclic buffer way, except the two channels

are concatenated, with channel 3 following channel 2 in the

cyclic sequence. During these buffer reads, if a buffer

position does not contain data, it is skipped. After each buffer

location is read it is cleared by the SPI1 logic.

Figure 18. SPI1 16-Bit Burst Transfer Example

Bit 7

Bit6

BIt5

Bit4

Bit3

Bit2

Bit1

Bit0

First TX Byte

R/W

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

Second TX Byte

Third TX Byte

Fourth TX Byte

Bit 7

Bit6

BIt5

Bit4

Bit3

Bit2

Bit1

Bit0

First RX Byte

Second RX Byte

SA3

SA2

SA1

SA0

Third RX Byte

Fourth RX Byte

SDS

RNE

ICL

FIX0

FIX1

b00 b01 b02 b03 b04 b05 b06 b07 b08 b09 b10 b11 b12 b13 b14 b15

CSB

SLCK

MISO

33781 Datasheet(PDF) 24 Page - Freescale Semiconductor, Inc

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