33781 datasheet(15/44 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33781

FUNCTIONAL DESCRIPTIONS

INTRODUCTION

FUNCTIONAL DESCRIPTIONS

INTRODUCTION

The 33781 is intended to be used as a master device in a

distributed system. It contains both protocol generators and

physical interfaces, to allow an MCU to communicate with

devices on the bus using two different SPI interfaces. Four

differential buses are provided. The physical layer uses a

two-wire bus to carry power and signal. The physical layer

uses wave-shaped voltage signals for commands from the

master and wave-shaped current signals for responses from

the slaves. The protocol and physical layer conform to the

DSI 2.02 specification.

The equivalent bus capacitance consists of capacitors

connected between the two bus wires and capacitors

between the bus wires and ground. Because the voltage

change on either of the bus wires to ground is only 1/2 the

amount of change between the two bus wires, the

capacitance to ground only conducts half as much current as

it would if connected directly across the bus. The equivalent

bus capacitance of a capacitor to ground from the bus wires

is one half of the actual amount of the capacitor. The amount

of capacitance from either bus wire to ground should be kept

the same in order to achieve the lowest radiated EMI energy.

The 2.2nF capacitors required between the bus wires and

ground result in an equivalent of 1.1nF of capacitance across

the bus as seen by either bus wire.

Table 5 shows the voltages used for operation. Low side

(LS) is the bus wire that is the most negative and high side

(HS) is the bus wire that is the most positive. Figure 5 shows

the bus waveforms in normal operation.

FUNCTIONAL PIN DESCRIPTIONS

RESET (RST)

When pulled low, this will reset all internal registers to a

known state as indicated in the section entitled SPI0 Register

and Bit Descriptions on page 29.

CHIP SELECT n (CSn)

This input is used to select the SPIn port when pulled to

ground. When high, the associated SPIn port signals are

ignored. The SPIn transaction is signaled as completed when

this signal returns high.

MASTER OUT/SLAVE IN 0 (MOSI0)

This is the SPI data input to the device. This data is

sampled on the positive (rising) edge of SCLK0. There is no

MOSI pin or function for SPI1.

SERIAL CLOCK (SCLKn)

This is the clock signal from the SPIn master device. It

controls the clocking of data to SPIn and data reads from the

SPIn.

MASTER IN/SLAVE OUT (MISOn)

This is the SPIn data from SPIn to the SPIn master. Data

changes on the negative (falling) transition of the associated

SCLKn.

CLOCK (CLK)

This is the main clock source for the internal logic. It must

be 4.0MHz.

GROUND (GND)

Ground source for DSI/DBUS return.

DIGITAL GROUND (VSS)

Ground source for logic.

DIGITAL GROUND AND IDDQ (VSS_IDDQ)

Used for IDDQ testing during IC manufacturing test.

ANALOG GROUND (AGND)

Ground source for analog circuits.

POWER SOURCE (VCC)

Nominal +5.0V Regulated Input.

DIGITAL REGULATOR OUTPUT (VDD)

Nominal +2.5V internal regulator Pin. This must be

bypassed with a small capacitor to ground (100nF)

Table 5. High Side and Low Side Typical Voltages (Voltage Relative to Ground)

Low Side

High Side

IDLE

HIGH

LOW

IDLE

HIGH

LOW

Vmid-2.25 (16)

Vmid-0.75 (16)

VSUPn

Vmid+2.25 (16)

Vmid+0.75 (16)

Notes

16.

VMID = VSUPn/2.

33781 Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc

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