33781 datasheet(3/44 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33781

PIN CONNECTIONS

Figure 3. 33781 Pin Connections

Table 1. 33781 Pin Definitions

A functional description of each Pin can be found in the Functional Pin Descriptions section beginning on page 15.

Pin Name

Pin Function

Formal Name

Definition

RST

Reset

IC Reset

A low level on this pin returns all registers to a known state as indicated

in the sections entitled SPI0 Register and Bit Descriptions and SPI1

Communications.

SCLK0

Input

SPI0 Serial Data Clock Clocks data in from and out to SPI0. MISO0 data changes on the negative

transition of SCLK0. MOSI0 is sampled on the positive edge of SCLK0.

MOSI0

Input

SPI0 Master Out Slave

SPI data into SPI0. This data input is sampled on the positive edge of

SCLK0

MISO0

Output

SPI0 Master In Slave

Out

SPI0 data sent to the MCU by this device. This data output changes on

the negative edge of SCLK0. When CS0 is high, this Pin is high-

impedance.

SCLK1

Input

SPI1 Serial Data Clock Clocks data out from SPI1. MISO1 data changes on the negative

transition of SCLK1.

MISO1

Output

SPI1 Master In Slave

Out

SPI1 data sent to the MCU by this device. This data output changes on

the negative edge of SCLK1. When CS1 is high, this Pin is high-

impedance.

CS0

Input

SPI0 Chip Select

When this signal is high, SPI signals on SPI0 are ignored. Asserting this

pin low starts an SPI0 transaction. The SPI0 transaction is signaled as

completed when this signal returns high.

AGND

Ground

Analog Ground

Ground for the analog circuits. This pin is not connected internally to the

other grounds on the chip. It should be connected to a quiet ground on

the board.

CS1

Input

SPI1 Chip Select

When this signal is high, SPI signals on SPI1 are ignored. Asserting this

pin low starts an SPI1 transaction. The SPI1 transaction is signaled as

completed when this signal returns high.

VSS

Ground

Digital Ground

Digital ground connected internally to the other on-chip grounds. This

ground is connected to circuits that will consume current during IDDQ

testing.

VDD

Power

Digital Voltage

Output of the Internal 2.5V regulator for the digital circuits. No external

current draw is allowed from this pin.

RST

SCLK0

MOSI0

MISO0

SCLK1

MISO1

CS0

AGND

CS1

VSS

VDD

VPP

VCC

CLK

TESTIN

TESTOUT

VSS_IDDQ

GND

D3L

D3H

VSUP2

D2H

D2L

GND

D1L

D1H

VSUP1

D0H

DPH

D0L

DPL

GND

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