33894 datasheet(21/28 Pages) FREESCALE

21 / 28 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33894

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

ADDRESS A1A0011—CURRENT DETECTION TIME

AND OPEN LOAD REGISTER (CDTOLR)

The CDTOLR register is used by the MCU to determine

the amount of time the device will allow an overcurrent low

condition before an output latches OFF. Each output is

independently selected for configuration based on A1A0,

which are the state of the D12:D11 bits (refer to Table 9,

page 20).

Bits D1:D0 (OCLT1_s:OCLT0_s) allow the MCU to select

one of three overcurrent fault blanking times defined in

Table 12. Note that these timeouts apply only to the

overcurrent low detection levels. If the selected overcurrent

high level is reached, the device will latch off within 20

µs.

A logic [1] on bit D2 (OCL_DIS_s) disables the overcurrent

low detection feature. When disabled, there is no timeout for

the selected output and the overcurrent low detection feature

is disabled.

A logic [1] on bit D3 (OL_DIS_s) disables the open load

(OL) detection feature for the output corresponding to the

state of bits D12:D11.

ADDRESS A1A0100—DIRECT INPUT CONTROL

The DICR register is used by the MCU to enable, disable,

or configure the direct IN pin control of each output. Each

output is independently selected for configuration based on

the state bits D12:D11 (refer to Table 9, page 20).

For the selected output, a logic [0] on bit D1 (DIR_DIS_s)

will enable the output for direct control. A logic [1] on bit D1

will disable the output from direct control.

While addressing this register, if the Input was enabled for

direct control, a logic [1] for the D0 (A/O_s) bit will result in a

Boolean AND of the IN pin with its corresponding IN_SPI

D4:D0 message bit when addressing OCR0. Similarly, a

logic [0] on the D0 pin results in a Boolean OR of the IN pin

to the corresponding message bits when addressing the

OCR0. This register is especially useful if several loads are

required to be independently PWM controlled. For example,

the IN pins of several devices can be configured to operate

all of the outputs with one PWM output from the MCU. If each

output is then configured to be Boolean ANDed to its

respective IN pin, each output can be individually turned OFF

by SPI while controlling all of the outputs, commanded on

with the single PWM output.

A logic [1] on bit D2 (CSNS_high_s) is used to select the

high ratio on the CSNS pin for the selected output. The

default value [0] is used to select the low ratio (Table 13).

A logic [1] on bit D3 (FAST_SR_s) is used to select the

high speed slew rate for the selected output, the default

value [0] corresponds to the low speed slew rate.

ADDRESS X0101—UNDERVOLTAGE/

OVERVOLTAGE REGISTER (UOVR)

The UOVR register disables the undervoltage (D1) and/or

overvoltage (D0) protection. When these two bits are

logic [0], the undervoltage and overvoltage are active (default

value).

Table 10. Overcurrent Low Detection Levels

SOCL2_s

(D2)

SOCL1_s

(D1)

SOCL0_s

(D0)

Overcurrent Low

Detection (Amperes)

HS0:HS3

9.1

8.15

7.2

6.25

5.25

4.3

3.35

2.4

* “_s” refers to the output, which is selected through bits D12:D11;

refer to Table 9, page 20.

Table 11. Overcurrent High Detection Levels

SOCH_s

* (D3)

Overcurrent High Detection (Amperes)

HS0:HS3

* “_s” refers to the output, which is selected through bits D12:D11;

refer to Table 9, page 20.

Table 12. Overcurrent Low Detection Blanking Time

OCLT[1:0]_s

Timing

155 ms

Do not use

75 ms

150

µs

* “_s” refers to the output, which is selected through bits D12 :D11;

refer to Table 9, page 20.

Table 13. Current Sense Ratio

CSNS_high_s

* (D2)

Current Sense Ratio

HS0:HS3

1/6500

1/20000

* “_s” refers to the output, which is selected through bits D12 :D11;

refer to Table 9, page 20.

33894 Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc

33894 Datasheet(HTML) 21 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL