33894 datasheet(10/28 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33894

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.5 V

≤ V

DD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted.

Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING HS0:HC3

Output Rising Slow Slew Rate A (DICR D3 = 0) (18)

9.0 V < VPWR < 16 V

SRRA_SLOW

0.1

0.3

0.5

µs

Output Rising Slow Slew Rate B (DICR D3 = 0) (19)

9.0 V < VPWR < 16 V

SRRB_SLOW

0.015

0.05

0.15

µs

Output Rising Fast Slew Rate A (DICR D3 = 1) (18)

9.0 V < VPWR < 16 V

SRRA_FAST

0.2

0.5

1.5

µs

Output Rising Fast Slew Rate B (DICR D3 = 1) (19)

9.0 V < VPWR < 16 V

SRRB_FAST

0.015

0.05

0.5

µs

Output Falling Slow Slew Rate A (DICR D3 = 0) (18)

9.0 V < VPWR < 16 V

SRFA_SLOW

0.1

0.3

0.5

µs

Output Falling Slow Slew Rate B (DICR D3 = 0) (19)

9.0 V < VPWR < 16 V

SRFB_SLOW

0.015

0.05

0.15

µs

Output Falling Fast Slew Rate A (DICR D3 = 1) (18)

9.0 V < VPWR < 16 V

SRFA_FAST

0.4

1.0

2.0

µs

Output Falling Fast Slew Rate B (DICR D3 = 1) (19)

9.0 V < VPWR < 16 V

SRFB_FAST

0.05

0.175

0.6

µs

Output Turn-ON Delay Time in Fast/Slow Slew Rate (20)

DICR = 0, DICR = 1

tDLY(ON)

2.0

200

µs

Output Turn-OFF Delay Time in Slow Slew Rate Mode (21)

DICR = 0

tDLY_SLOW(O

FF)

460

1000

µs

Output Turn-OFF Delay Time in Fast Slew Rate Mode (21)

DICR = 1

tDLY_FAST(O

FF)

120

400

µs

Overcurrent Low Detection Blanking Time (OCLT[1:0])

01 (22)

tOCL0

tOCL1

tOCL2

tOCL3

108

–

0.08

155

–

0.15

202

–

0.25

Notes

18.

Rise and Fall Slew Rates A measured across a 5.0

Ω resistive load at high-side output = 0.5 V to V

PWR- 3.5 V (see Figure 4, page 13).

These parameters are guaranteed by process monitoring.

19.

Rise and Fall Slew Rates B measured across a 5.0

Ω resistive load at high-side output = 0.5 V to V

PWR- 3.5 V (see Figure 4). These

parameters are guaranteed by process monitoring.

20.

Turn-ON delay time measured from rising edge of any signal (IN[0:3], SCLK, CS) that would turn the output ON to VHS[0:3] = 0.5 V with

RL = 5.0 Ω resistive load.

21.

Turn-OFF delay time measured from falling edge of any signal (IN[0:3], SCLK, CS) that would turn the output OFF to VHS[0:3] = VPWR-

0.5 V with RL = 5.0 Ω resistive load.

22.

This logical bit is not defined. Do not use.

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