Analog Integrated Circuit Device Data

4

Freescale Semiconductor

33894

PIN CONNECTIONS

10

CS

Chip Select

(Active Low)

This input pin is connected to a chip select output of a master MCU. The MCU

determines which device is addressed (selected) to receive data by pulling the CS pin

of the selected device logic LOW, thereby enabling SPI communication with the device.

Other unselected devices on the serial link having their CS pins pulled up logic HIGH

disregard the SPI communication data sent. This pin has an active internal pullup

current source and requires CMOS logic levels.

11

SCLK

Serial Clock

This input pin is connected to the MCU providing the required bit shift clock for SPI

communication. It transitions one time per bit transferred at an operating frequency,

serial clock signal is idle between command transfers. The signal is used to shift data

into and out of the device. This pin has an active internal pulldown current source.

12

SI

Serial Input

This pin is a command data input pin connected to the SPI Serial Data Output of the

microcontroller (MCU) or to the SO pin of the previous device of a daisy

devices. The input requires CMOS logic level signals and incorporates an internal

active pulldown. Device control is facilitated by the input's receiving the MSB first of a

serial 8-bit control command. The MCU ensures data is available upon the falling edge

of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit

command into the internal command shift register. This pin has an active internal

pulldown current source.

13

V

DD

Digital Drain Voltage

(Power)

This pin is an external voltage input pin used to supply power to the SPI circuit. In the

limited functionality of the device.

14, 17, 23

GND

Ground

These pins are the ground for the logic and analog circuitry of the device.

15

V

PWR

Positive Power Supply

This pin connects to the positive power supply and is the source of operational power

16

SO

Serial Output

This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin

of the next device of a daisy

impedance OFF condition) so long as the CS pin of the device is logic HIGH. SO is only

active when the CS pin of the device is asserted logic LOW. The generated SO output

signals are CMOS logic levels. SO output data is available on the falling edge of SCLK

and transitions immediately on the rising edge of SCLK.

18

19

21

22

HS3

HS1

HS0

HS2

High-Side Outputs

Protected 35 m

Ω high-side power output pins to the load.

24

FSI

Fail-Safe Input

The value of the resistance connected between this pin and ground determines the

state of the outputs after a Watchdog timeout occurs. Depending on the resistance

value, either all outputs are OFF or the output HSO only is ON. If the FSI pin is left to

float up to a logic [1] level, then the outputs HS0 and HS2 will turn ON when in the Fail-

Safe state. When the FSI pin is connected to GND, the Watchdog circuit and Fail-Safe

operation are disabled. This pin incorporates an active internal pullup current source.

Table 1. 33894 Pin Definitions (continued)

Pin Number

Pin Name

Formal Name

Definition