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33894 Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc

Part # 33894
Description  Quad High-Side Switch
PDF  28 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

33894 Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
Freescale Semiconductor
3
33894
PIN CONNECTIONS
PIN CONNECTIONS
Figure 3. 33894 Pin Connections
Table 1. 33894 Pin Definitions
Functional descriptions of many of these pins can be found in Functional Description on page 16.
Pin Number
Pin Name
Formal Name
Definition
1
CSNS
Output Current
Monitoring
The Current Sense pin sources a current proportional to the designated HS0:HS3
output. That current is fed into a ground-referenced resistor and its voltage is monitored
by an MCU's A/D. The output to be monitored is selected via the SPI. This pin can be
tri-stated through SPI.
2
3
5
6
IN0
IN1
IN2
IN3
Serial Inputs
The IN0:IN3 high-side input pins are used to directly control HS0:HS3 high-side output
pins, respectively. An SPI register determines if each input is activated or if the input
logic state is ORed or ANDed with the SPI instruction. These pins are to be driven with
5.0 V CMOS levels, and they have an active internal pulldown current source.
4, 20
NC
No Connect
These pins may not be connected.
7
FS
Fault Status
(Active Low)
This pin is an open drain configured output requiring an external pullup resistor to VDD
for fault reporting. If a device fault condition is detected, this pin is active LOW. Specific
device diagnostic faults are reported via the SPI SO pin.
8
WAKE
Wake
This input pin controls the device mode and watchdog timeout feature if enabled. An
internal clamp protects this pin from high damaging voltages when the output is current
limited with an external resistor. This input has a passive internal pulldown.
9
RST
Reset
This input pin is used to initialize the device configuration and fault registers, as well as
place the device in a low-current sleep mode. The pin also starts the watchdog timer
when transitioning from logic [0] to logic [1]. This pin should not be allowed to be
logic [1] until VDD is in regulation. This pin has a passive internal pulldown.
Transparent Top View of Package
13
24
12
10
9
8
7
6
5
4
3
2
1
11
23
22
19
20
21
16
17
18
15
14
SO
GND
HS3
HS1
NC
HS0
HS2
GND
FSI
GND
V
PWR



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