LPC1763 datasheet(17/79 Pages) NXP

17 / 79 page

LPC1769_68_67_66_65_64_63

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Product data sheet

Rev. 7 — 5 April 2011

17 of 79

NXP Semiconductors

LPC1769/68/67/66/65/64/63

32-bit ARM Cortex-M3 microcontroller

[4]

Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide

output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.

Open-drain configuration applies to all functions on this pin.

[5]

Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and

Low-speed mode only). This pad is not 5 V tolerant.

[6]

5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

[7]

5 V tolerant pad with TTL levels and hysteresis. Internal pull-up and pull-down resistors disabled.

[8]

5 V tolerant pad with TTL levels and hysteresis and internal pull-up resistor.

[9]

5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

[10] Pad provides special analog functionality.

[11] When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding

is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

[12] When the RTC is not used, connect VBAT to VDD(REG)(3V3) and leave RTCX1 floating.

LPC1763 Datasheet(PDF) 17 Page - NXP Semiconductors