LPC1763 datasheet(16/79 Pages) NXP

16 / 79 page

LPC1769_68_67_66_65_64_63

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 5 April 2011

16 of 79

NXP Semiconductors

LPC1769/68/67/66/65/64/63

32-bit ARM Cortex-M3 microcontroller

[1]

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[2]

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,

digital section of the pad is disabled and the pin is not 5 V tolerant.

[3]

5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,

digital section of the pad is disabled.

TDI

2[1][8]

C3[1][8]

TDI — Test Data in for JTAG interface.

TMS/SWDIO

3[1][8]

B1[1][8]

TMS — Test Mode Select for JTAG interface.

I/O

SWDIO — Serial wire debug data input/output.

TRST

4[1][8]

C2[1][8]

TRST — Test Reset for JTAG interface.

TCK/SWDCLK

5[1][7]

C1[1][7]

TCK — Test Clock for JTAG interface.

SWDCLK — Serial wire clock.

RTCK

100[1][7]

B2[1][7]

RTCK — JTAG interface control signal.

RSTOUT

RSTOUT — This is a 3.3 V pin. LOW on this pin indicates the

microcontroller being in Reset state.

RESET

17[9]

F3[9]

External reset input: A LOW on this pin resets the device, causing I/O

ports and peripherals to take on their default states, and processor

execution to begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

22[10][11]

H2[10][11]

Input to the oscillator circuit and internal clock generator circuits.

XTAL2

23[10][11]

G3[10][11]

Output from the oscillator amplifier.

RTCX1

16[10][12]

F2[10][11]

Input to the RTC oscillator circuit.

RTCX2

18[10]

G1[10]

Output from the RTC oscillator circuit.

VSS

31, 41,

55, 72,

83, 97[10]

B3, B7,

C9, G7,

J6, K3[10]

ground: 0 V reference.

VSSA

11[10]

E1[10]

analog ground: 0 V reference. This should nominally be the same

voltage as VSS, but should be isolated to minimize noise and error.

VDD(3V3)

28, 54,

71, 96[10]

K2, H9,

C10,

A3[10]

3.3 V supply voltage: This is the power supply voltage for the I/O

ports.

VDD(REG)(3V3)

42, 84[10]

H6, A7[10] I

3.3 V voltage regulator supply voltage: This is the supply voltage for

the on-chip voltage regulator only.

VDDA

10[10]

E2[10]

analog 3.3 V pad supply voltage: This should be nominally the same

voltage as VDD(3V3) but should be isolated to minimize noise and error.

This voltage is used to power the ADC and DAC. This pin should be

tied to 3.3 V if the ADC and DAC are not used.

VREFP

12[10]

E3[10]

ADC positive reference voltage: This should be nominally the same

voltage as VDDA but should be isolated to minimize noise and error.

Level on this pin is used as a reference for ADC and DAC. This pin

should be tied to 3.3 V if the ADC and DAC are not used.

VREFN

ADC negative reference voltage: This should be nominally the same

voltage as VSS but should be isolated to minimize noise and error.

Level on this pin is used as a reference for ADC and DAC.

VBAT

19[10][12]

G2[10][12]

RTC pin power supply: 3.3 V on this pin supplies the power to the

RTC peripheral.

n.c.

D4, E4

not connected.

Table 4.

Pin description …continued

Symbol

Ball

Type

Description

LPC1763 Datasheet(PDF) 16 Page - NXP Semiconductors

LPC1763 Datasheet(HTML) 16 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Download

Link URL