LPC1763 datasheet(59/79 Pages) NXP

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LPC1769_68_67_66_65_64_63

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Product data sheet

Rev. 7 — 5 April 2011

59 of 79

NXP Semiconductors

LPC1769/68/67/66/65/64/63

32-bit ARM Cortex-M3 microcontroller

11.8 USB interface

Remark: The USB controller is available as a device/Host/OTG controller on parts

LPC1769/68/66/65 and as device-only controller on part LPC1764.

[1]

Characterized but not implemented as production test. Guaranteed by design.

Table 16.

Dynamic characteristics: USB pins (full-speed)

CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(3V3); 3.0 V ≤ VDD(3V3) ≤ 3.6 V.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

rise time

10 % to 90 %

8.5

13.8

fall time

10 % to 90 %

7.7

13.7

tFRFM

differential rise and fall time

matching

tr /tf

109

VCRS

output signal crossover voltage

1.3

2.0

tFEOPT

source SE0 interval of EOP

see Figure 21

160

175

tFDEOP

source jitter for differential transition

to SE0 transition

see Figure 21

−2-

tJR1

receiver jitter to next transition

−18.5

+18.5

tJR2

receiver jitter for paired transitions

10 % to 90 %

−9-

tEOPR1

EOP width at receiver

must reject as

EOP; see

Figure 21

[1] 40

--ns

tEOPR2

EOP width at receiver

must accept as

EOP; see

Figure 21

[1] 82

--ns

Fig 21. Differential data-to-EOP transition skew and EOP width

002aab561

TPERIOD

differential

data lines

crossover point

source EOP width: tFEOPT

receiver EOP width: tEOPR1, tEOPR2

crossover point

extended

differential data to

SE0/EOP skew

× TPERIOD + tFDEOP

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