DS26324 datasheet(18/120 Pages) MAXIM

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DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit

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Figure 5-3. Serial Port Operation for Read Access with CLKE = 1

SCLK

SDI

SDO

CSB

(lsb)

(msb)

(lsb)

(msb)

5.1.2

Parallel Port Operation

When using the parallel interface on the DS26324 the user has the option for either multiplexed bus operation or

nonmultiplexed bus operation. The ALE pin is pulled high in nonmultiplexed bus operation. The DS26324 can

operate with either Intel or Motorola bus-timing configurations selected by MOTEL pin. This pin being high selects

the Intel mode. The parallel port is only operational if MODESEL pin is pulled high. The following Table lists all the

pins and their functions in the parallel port mode. See the timing diagrams in Section 9 for more details.

Table 5-1. Parallel Port Mode Selection and Pin Functions

MODESEL, MOTEL,

MUX

PARALLEL HOST

INTERFACE

ADDRESS, DATA, AND CONTROL

100

Nonmultiplexed Motorola

CSB, ACKB, DSB, RWB, ASB, A[5:0], D[7:0], INTB

110

Nonmultiplexed Intel

CSB, RDYB, WRB, RDB, ALE, A[5:0], D[7:0], INTB

101

Multiplexed Motorola

CSB, ACKB, DSB, RWB, ASB, AD[7:0], INTB

111

Multiplexed Intel

CSB, RDYB, WRB, RDB, ALE, AD[7:0], INTB

5.1.3

Interrupt Handling

There are four sets of events that can potentially trigger an Interrupt. The interrupt functions as follows:

•

When status changes on an interruptible event, INTB pin will go low if the event is enabled through the

corresponding Interrupt Enable Register. The INTB has to be pulled high externally with a 10k

Ω resister for

wired-OR operation. If a wired-OR operation is not required, the INTB pin can be configured to be high when

not active by setting register GISC.INTM.

•

When an Interrupt occurs the Host Processor has to read the Interrupt Status register to determine the source

of the Interrupt. The read will also clear the Interrupt Status register and this will clear the output INTB pin. The

Interrupt Status register can also be configured as clear on write as per register GISC.CWE. When set to clear

on write, and interrupt status register bit (and the interrupt it generates) will only be cleared on writing a ‘1’ to

it’s bit location in the interrupt status register. This makes is possible to clear interrupts on some bits in a

•

Subsequently the host processor can read the corresponding Status Register to check the real-time status of

the event.

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