DS26324 datasheet(21/120 Pages) MAXIM

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DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit

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Table 5-2. Telecommunications Specification Compliance for DS26324 Transmitters

TRANSMITTER FUNCTION

TELECOMMUNICATIONS COMPLIANCE

AMI Coding, B8ZS Substitution, DS1 Electrical Interface

ANSI T1.102

T1 Telecom Pulse Mask compliance

ANSI T1.403

T1 Telecom Pulse Mask compliance

ANSI T1.102

Transmit Electrical Characteristics for E1 Transmission

and Return Loss Compliance

ITU-T G.703

Table 5-3. Registers Related to Control of DS26324 Transmitters

NAME

FUNCTION

Transmit All Ones Enable

TAOE

Transmit all ones enable.

Driver Fault Monitor Status

DFMS

Driver fault status.

Driver Fault Monitor Interrupt Enable

DFMIE

Driver fault status interrupt mask.

Driver Fault Monitor Interrupt Status

DFMIS

Driver fault status interrupt mask.

Automatic Transmit All Ones Select

ATAOS

Transmit all ones enabled automatically on LOS.

Global Configuration

Global control of jitter attenuator, line coding and short

circuit protection.

Template Select Transmitter

TST

The transmitter that the Template Select Transmitter

Template Select

The TS2 to TS0 bits for selection of the templates for

transmitter and TIMPOFF and TIMPRIM bits to control

transmit impedance match.

Output Enable Configuration

These register bits can be used to enable the transmitter

outputs.

Master Clock Selection

Selects the MCLK frequency used for transmit and

receive.

Single-Rail Mode Select

SRMS

This register can be used to select between single-rail

and dual-rail mode.

Line Code Selection

LCS

The individual transceiver line codes can be selected to

overwrite the global setting.

Transmit Power-Down Enable

TPDE

Individual transmitters can be powered down.

Individual Jitter Attenuator Enable

IJAE

Enables the jitter attenuator.

Individual Jitter Attenuator Position

Select

IJAPS

Selects whether jitter attenuator is in transmit or receive

path

Individual Jitter Attenuator FIFO

Depth Select

IJAFDS

Selects depth of jitter attenuator FIFO.

Individual Jitter Attenuator FIFO

Limit Trip

IJAFLT

Indicates jitter attenuator FIFO within 4 bits of its useful

limit.

Individual Short-Circuit Protection

Disable

ISCPD

This register allows the individual transmitters to have

short-circuit protection disable.

Bit Error Rate Tester Control

BTCR

This register allows mapping of the internal BERTs into

an individual transmit path.

Transmit Clock Invert

TCLKI

Inverts TCLK input.

BPV Error Insertion

BEIR

Inserts a bipolar error in the transmit path when in single-

rail mode.

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