MAX2832 datasheet(21/33 Pages) MAXIM

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2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA,

and Rx/Tx/Antenna Diversity Switch

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an antenna diversity path between the ANT2 port (pins

9 and 10) and the receiver. When RXTX = 1, the PA

and transmit path are automatically connected to the

ANT2 port, regardless of the logic state of ANTSEL. For

solutions not requiring antenna diversity, set ANTSEL

logic-level high, enabling only the ANT2 port for both

receive and transmit modes.

The ANT1 and ANT2 differential ports are internally AC-

coupled and internally matched to 100

Ω. Directly con-

nect 2:1 baluns or balanced bandpass filters (BPFs) to

these ports for applications requiring antenna diversity.

For applications not requiring antenna diversity, only a

single balun or balanced BPF is required on the ANT2

port, and the ANT1 port can be left open. Provide elec-

trically symmetrical input traces to the baluns to main-

tain IP2 and RF common-mode noise rejection for the

receiver, and to maintain a balanced load for the PA.

Receiver

After the switch, the receiver integrates an LNA and VGA

with a 95dB digitally programmable gain control range,

direct-conversion downconverters, I/Q baseband low-

pass filters with programmable LPF corner frequencies,

analog RSSI and integrated DC-offset correction circuitry.

A logic-low on the RXTX input (pin 48) and a logic-high on

the SHDN input (pin 12) enable the receiver.

LNA Gain Control

The LNA has three gain modes: max gain, max gain

-16dB, and max gain -33dB. The three LNA gain

modes can be serially programmed through the SPI™

interface by programming bits D6:D5 in Register 11

(A3:A0 = 1011) or programmed in parallel through the

digital logic gain-control pins, B7 (pin 6) and B6 (pin 3).

Set bit D12 = 1 in Register 8 (A3:A0 = 1000) to enable

programming through the SPI interface, or set bit D12 =

0 to enable parallel programming. See Table 2 for LNA

gain-control settings.

Baseband Variable-Gain Amplifier

The receiver baseband variable-gain amplifiers provide

62dB of gain control range programmable in 2dB steps.

The VGA gain can be serially programmed through the

SPI interface by setting bits D4:D0 in Register 11 (A3:A0

= 1011) or programmed in parallel through the digital

logic gain-control pins, B5 (pin 14), B4 (pin 34), B3 (pin

8), B2 (pin 11), and B1 (pin 23). Set bit D12 = 1 in

through the serial interface or set bit D12 = 0 to enable

parallel programming through the external logic pins.

See Table 3 for the gain-step value and Table 4 for

baseband VGA gain-control settings.

Receiver Baseband Lowpass Filter

The receiver integrates lowpass filters that provide an

upper -3dB corner frequency of 8.5MHz (nominal mode)

with 50dB of attenuation at 20MHz, and 45ns of group

delay ripple in the passband (10kHz to 8.5MHz). The

upper -3dB corner frequency is tightly controlled on-chip

and does not require user adjustment. However, provi-

sions are made to allow fine tuning of the upper -3dB

Table 3. Receiver Baseband VGA Gain-

Step Value (Pins B5:B1 or Register D4:D0,

A3:A0 = 1011)

Table 4. Baseband VGA Gain-Control

Settings in Receiver Gain-Control Register

(Pin B5:B1 or Register D4:D0, A3:A0 = 1011)

Table 5. Receiver LPF Coarse -3dB

Corner Frequency Settings in Register

(A3:A0 = 1000)

PIN/BIT

GAIN STEP (dB)

B1/D0

B2/D1

B3/D2

B4/D3

B5/D4

B5:B1 OR D4:D0

GAIN

11111

Max

11110

Max - 2dB

11101

Max - 4dB

00000

Min

BITS (D1:D0)

-3dB CORNER

FREQUENCY (MHz)

MODE

7.5

11b

8.5

11g

Turbo 1

Turbo 2

Table 2. LNA Gain-Control Settings (Pins

B7:B6 or Register A3:A0 = 1011, D6:D5)

B7 OR D6

B6 OR D5

NAME

DESCRIPTION

High

Max gain

Medium

Max gain - 16dB (typ)

Low

Max gain - 33dB (typ)

SPI is a trademark of Motorola, Inc.

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