AD5757ACPZ datasheet(32/44 Pages) AD

32 / 44 page

AD5757

Rev. A | Page 32 of 44

Status Register

The status register is a read only register. This register contains

any fault information as a well as a ramp active bit and a user

toggle bit. When the STATREAD bit in the main control

the SDO pin during every write sequence. Alternatively, if the

STATREAD bit is not set, the status register can be read using

the normal readback operation.

Table 28. Decoding the Status Register

MSB

LSB

D15

D14

D13

D12

D11

D10

DC-

DCD

DC-

DCC

DC-

DCB

DC-

DCA

User

toggle

PEC

error

Ramp

active

Over

TEMP

IOUT_D

fault

IOUT_C

fault

IOUT_B

fault

IOUT_A

fault

1 X = don’t care.

Table 29. Status Register Options

Bit

Description

DC-DCD

This bit is set on Channel D if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX

voltage). In this case, the IOUT_D fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more

information on this bit’s operation under this condition.

DC-DCC

This bit is set on Channel C if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX

voltage). In this case, the IOUT_C fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more

information on this bit’s operation under this condition.

DC-DCB

This bit is set on Channel B if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX

voltage). In this case, the IOUT_B fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more

information on this bit’s operation under this condition.

DC-DCA

This bit is set on Channel A if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX

voltage). In this case, the IOUT_A fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more

information on this bit’s operation under this condition.

User toggle

User toggle bit. This bit is set or cleared via the software register. This can be used to verify data communications if

needed.

PEC Error

Denotes a PEC error on the last data-word received over the SPI interface.

Ramp Active

This bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one channel).

Over TEMP

This bit is set if the AD5757 core temperature exceeds approximately 150°C.

IOUT_D Fault

This bit is set if a fault is detected on the IOUT_D pin.

IOUT_C Fault

This bit is set if a fault is detected on the IOUT_C pin.

IOUT_B Fault

This bit is set if a fault is detected on the IOUT_B pin.

IOUT_A Fault

This bit is set if a fault is detected on the IOUT_A pin.

AD5757ACPZ Datasheet(PDF) 32 Page - Analog Devices

AD5757ACPZ Datasheet(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL