AD5757ACPZ datasheet(35/44 Pages) AD

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AD5757

Rev. A | Page 35 of 44

Digitally controlling the slew rate of the output is necessary to

meet the analog rate of change requirements for HART.

DIGITAL SLEW RATE CONTROL

The slew rate control feature of the AD5757 allows the user to

control the rate at which the output value changes. With the

slew rate control feature disabled, the output value changes at a

rate limited by the output drive circuitry and the attached load.

To reduce the slew rate, this can be achieved by enabling the

slew rate control feature. With the feature enabled via the SREN

bit of the slew rate control register (see Table 25), the output,

instead of slewing directly between two values, steps digitally at

a rate defined by two parameters accessible via the slew rate

control register, as shown in Table 25. The parameters are

SR_CLOCK and SR_STEP. SR_CLOCK defines the rate at

which the digital slew is updated, for example, if the selected

update rate is 8 kHz, the output updates every 125 μs. In conjunc-

tion with this, SR_STEP defines by how much the output value

changes at each update. Together, both parameters define the

rate of change of the output value. Table 31 and Table 32 outline

the range of values for both the SR_CLOCK and SR_STEP

parameters.

Table 31. Slew Rate Update Clock Options

SR_CLOCK

Update Clock Frequency (Hz)1

0000

64 k

0001

32 k

0010

16 k

0011

8 k

0100

4 k

0101

2 k

0110

1 k

0111

500

1000

250

1001

125

1010

1011

1100

1101

1110

1111

0.5

1 These clock frequencies are divided down from the 13 MHz internal

oscillator. See Table 1, Figure 46, and Figure 47.

Table 32. Slew Rate Step Size Options

SR_STEP

Step Size (LSBs)

000

001

010

011

100

101

110

128

111

256

The following equation describes the slew rate as a function of

the step size, the update clock frequency, and the LSB size:

Size

LSB

Frequency

Clock

Update

Size

Step

Change

Output

Time

Slew

where:

Slew Time

is expressed in seconds.

Output Change

is expressed in amps for IOUT_x.

When the slew rate control feature is enabled, all output

changes occur at the programmed slew rate (see the DC-to-DC

Converter Settling Time section for additional information).

For example, if the CLEAR pin is asserted, the output slews to

the clear value at the programmed slew rate (assuming that the

clear channel is enabled to be cleared). If a number of channels

are enabled for slew, care must be taken when asserting the

CLEAR pin. If one of the channels is slewing when CLEAR is

asserted, other channels may change directly to their clear

values not under slew rate control. The update clock frequency

for any given value is the same for all output ranges. The step

size, however, varies across output ranges for a given value of

step size because the LSB size is different for each output range.

POWER DISSIPATION CONTROL

The AD5757 contains integrated dynamic power control using

a dc-to-dc boost converter circuit, allowing reductions in power

consumption from standard designs.

In standard current input module designs, the load resistor

values can range from typically 50 Ω to 750 Ω. Output module

systems must source enough voltage to meet the compliance

voltage requirement across the full range of load resistor values.

For example, in a 4 mA to 20 mA loop when driving 20 mA, a

compliance voltage of >15 V is required. When driving 20 mA

into a 50 Ω load, only 1 V compliance is required.

The AD5757 circuitry senses the output voltage and regulates

this voltage to meet compliance requirements plus a small

headroom voltage. The AD5757 is capable of driving up to

24 mA through a 1 kΩ load.

DC-TO-DC CONVERTERS

The AD5757 contains four independent dc-to-dc converters.

These are used to provide dynamic control of the VBOOST supply

voltage for each channel (see Figure 49). Figure 56 shows the

discreet components needed for the dc-to-dc circuitry, and the

following sections describe component selection and operation

of this circuitry.

AVCC

LDCDC

DDCDC

CDCDC

4.7µF

CFILTER

0.1µF

RFILTER

CIN

SWx

VBOOST_X

≥10µF

10Ω

10µH

Figure 56. DC-to-DC Circuit

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