AD5757ACPZ datasheet(22/44 Pages) AD

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AD5757

Rev. A | Page 22 of 44

THEORY OF OPERATION

The AD5757 is a quad, precision digital-to-current loop

converter designed to meet the requirements of industrial

process control applications. It provides a high precision, fully

integrated, low cost, single-chip solution for generating current

loop outputs. The current ranges available are 0 mA to 20 mA,

0 mA to 24 mA, and 4 mA to 20 mA. The desired output

configuration is user selectable via the DAC control register.

On-chip dynamic power control minimizes package power

dissipation in current mode.

DAC ARCHITECTURE

The DAC core architecture of the AD5757 consists of two

matched DAC sections. A simplified circuit diagram is shown

in Figure 48. The four MSBs of the 16-bit data-word are

decoded to drive 15 switches, E1 to E15. Each of these switches

connects one of 15 matched resistors to either ground or the

reference buffer output. The remaining 12 bits of the data-word

drive Switch S0 to Switch S11 of a 12-bit voltage mode R-2R

ladder network.

8-/12-BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

S7/S11

E15

VOUT

Figure 48. DAC Ladder Structure

The voltage output from the DAC core is converted to a current

(see Figure 49), which is then mirrored to the supply rail so that

the application simply sees a current source output. The current

outputs are supplied by VBOOST_x.

16-BIT

DAC

VBOOST_x

IOUT_x

RSET

Figure 49. Voltage-to-Current Conversion Circuitry

Reference Buffers

The AD5757 can operate with either an external or internal

reference. The reference input requires a 5 V reference for

specified performance. This input voltage is then buffered

before it is applied to the DAC.

POWER-ON STATE OF THE AD5757

On power-up of the AD5757, the IOUT_x pins are in tristate mode.

SERIAL INTERFACE

The AD5757 is controlled over a versatile 3-wire serial interface

that operates at clock rates of up to 30 MHz and is compatible

with SPI, QSPI, MICROWIRE, and DSP standards. Data coding

is always straight binary.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the

device MSB first as a 24-bit word under the control of a serial

clock input, SCLK. Data is clocked in on the falling edge of SCLK.

If packet error checking, or PEC (see the Device Features

section), is enabled, an additional eight bits must be written to

the AD5757, creating a 32-bit serial interface.

There are two ways in which the DAC outputs can be updated:

individual updating or simultaneous updating of all DACs.

Individual DAC Updating

In this mode, LDAC is held low while data is being clocked into

the DAC data register. The addressed DAC output is updated on

the rising edge of SYNC. See

and

for timing

information.

Table 3

Figure 3

Simultaneous Updating of All DACs

In this mode, LDAC is held high while data is being clocked

into the DAC data register. Only the first write to each channel’s

DAC data register is valid after LDAC is brought high. Any subse-

quent writes while LDAC is still held high are ignored, although

they are loaded into the DAC data register. All the DAC outputs

are updated by taking LDAC low after SYNC is taken high.

VOUT_x

DAC

INTERFACE

LOGIC

OUTPUT

I/V AMPLIFIER

LDAC

SDO

SDIN

16-BIT

DAC

VREFIN

SYNC

DAC DATA

OFFSET

AND GAIN

CALIBRATION

DAC INPUT

SCLK

Figure 50. Simplified Serial Interface of Input Loading Circuitry

for One DAC Channel

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