AD5757

Rev. A | Page 30 of 44

Software Register

The software register has three functions. It allows the user to

perform a software reset to the part. It can be used to set the

user toggle bit, D11, in the status register. It is also used as part

of the watchdog feature when it is enabled. This feature is useful

to ensure that communication has not been lost between the

MCU and the AD5757 and that the datapath lines are working

properly (that is, SDIN, SCLK, and SYNC).

When the watchdog feature is enabled, the user must write

0x195 to the software register within the timeout period. If this

command is not received within the timeout period, the ALERT

pin signals a fault condition. This is only required when the

watchdog timer function is enabled.

DC-to-DC Control Register

The dc-to-dc control register allows the user control over

the dc-to-dc switching frequency and phase, as well as the

maximum allowable dc-to-dc output voltage. The dc-to-dc

control register options are shown in Table 23 and Table 24.

Table 21. Programming the Software Register

MSB

LSB

D15

D14

D13

D12

D11 to D0

1

0

0

User program

Reset code/SPI code

Table 22. Software Register Functions

Bit

Description

User Program

This bit is mapped to Bit D11 of the status register. When this bit is set to 1, Bit D11 of the status register is set

to 1. Likewise, when D12 is set to 0, Bit D11 of the status register is also set to zero. This feature can be used to

ensure that the SPI pins are working correctly by writing a known bit value to this register and reading back

the corresponding bit from the status register.

Reset Code/SPI Code

Option

Description

Reset code

Writing 0x555 to D[11:0] performs a reset of the AD5757.

SPI code

If the watchdog timer feature is enabled, 0x195 must be written to the software

register (D11 to D0) within the programmed timeout period.

Table 23. Programming the DC-to-DC Control Register

MSB

LSB

D15

D14

D13

D12 to D7

D6

D5 to D4

D3 to D2

D1 to D0

0

1

1

X1

DC-DC Comp

DC-DC phase

DC-DC Freq

DC-DC MaxV

Table 24. DC-to-DC Control Register Options

Bit

Description

DC-DC Comp

Selects between an internal and external compensation resistor for the dc-to-dc converter. See the DC-to-DC Converter

Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more

information.

0 = selects the internal 150 kΩ compensation resistor (default).

1 = bypasses the internal compensation resistor for the dc-to-dc converter. In this mode, an external dc-to-dc

capacitor to ground. Typically, a ~50 kΩ resistor is recommended.

DC-DC Phase

User programmable dc-to-dc converter phase (between channels).

00 = all dc-to-dc converters clock on the same edge (default).

01 = Channel A and Channel B clock on the same edge, Channel C and Channel D clock on opposite edges.

10 = Channel A and Channel C clock on the same edge, Channel B and Channel D clock on opposite edges.

11 = Channel A, Channel B, Channel C, and Channel D clock 90° out of phase from each other.

DC-DC Freq

DC-to-dc switching frequency; these are divided down from the internal 13 MHz oscillator (see Figure 46 and Figure 47).

00 = 250 ± 10% kHz.

01 = 410 ± 10% kHz (default).

10 = 650 ± 10% kHz.

DC-DC MaxV

00 = 23 V + 1 V/−1.5 V (default).

01 = 24.5 V ± 1 V.

10 = 27 V ± 1 V.

11 = 29.5 V ± 1V.