AD5757ACPZ datasheet(4/44 Pages) AD

4 / 44 page

AD5757

Rev. A | Page 4 of 44

SPECIFICATIONS

AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;

REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted.

Table 1.

Parameter1

Min

Typ

Max

Unit

Test Conditions/Comments

CURRENT OUTPUT

Output Current Ranges

Resolution

Bits

ACCURACY (EXTERNAL RSET)

Assumes ideal resistor

Total Unadjusted Error (TUE)

−0.05

±0.009

+0.05

% FSR

TUE Long-Term Stability

100

ppm FSR

Drift after 1000 hours, TJ = 150°C

Relative Accuracy (INL)

−0.006

+0.006

% FSR

Differential Nonlinearity (DNL)

−1

LSB

Guaranteed monotonic

Offset Error

−0.05

±0.005

+0.05

% FSR

Offset Error Drift2

±4

ppm FSR/°C

Gain Error

−0.05

±0.004

+0.05

% FSR

Gain TC2

±3

ppm FSR/°C

Full-Scale Error

−0.05

±0.008

+0.05

% FSR

Full-Scale TC2

±5

ppm FSR/°C

DC Crosstalk

0.0005

% FSR

External RSET

ACCURACY (INTERNAL RSET)

Total Unadjusted Error (TUE)3, 4

−0.14

+0.14

% FSR

−0.11

±0.009

+0.11

% FSR

TA = 25°C

TUE Long-Term Stability

180

ppm FSR

Drift after 1000 hours, TJ = 150°C

Relative Accuracy (INL)

−0.006

+0.006

% FSR

−0.004

+0.004

% FSR

TA = 25°C

Differential Nonlinearity (DNL)

−1

LSB

Guaranteed monotonic

Offset Error3, 4

−0.05

+0.05

% FSR

−0.04

±0.007

+0.04

% FSR

TA = 25°C

Offset Error Drift2

±6

ppm FSR/°C

Gain Error

−0.12

+0.12

% FSR

−0.06

±0.002

+0.06

% FSR

TA = 25°C

Gain TC2

±9

ppm FSR/°C

Full-Scale Error3, 4

−0.14

+0.14

% FSR

−0.1

±0.007

+0.1

% FSR

TA = 25°C

Full-Scale TC2

±14

ppm FSR/°C

DC Crosstalk4

−0.011

% FSR

Internal RSET

OUTPUT CHARACTERISTICS2

Current Loop Compliance Voltage

VBOOST_x −

2.4

VBOOST_x −

2.7

Output Current Drift vs. Time

Drift after 1000 hours, ¾ scale output, TJ = 150°C

ppm FSR

External RSET

140

ppm FSR

Internal RSET

Resistive Load

1000

The dc-to-dc converter has been characterized

with a maximum load of 1 kΩ

, chosen such that

compliance is not exceeded; see

Figure 31 and

DC-DC MaxV bits in

Table 24

Output Impedance

100

MΩ

DC PSRR

0.02

μA/V

REFERENCE INPUT/OUTPUT

Reference Input2

Reference Input Voltage

4.95

5.05

For specified performance

DC Input Impedance

150

MΩ

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