LPC178X datasheet(44/117 Pages) NXP

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LPC178X_7X

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Objective data sheet

Rev. 2 — 27 May 2011

44 of 117

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

7.8 Nested Vectored Interrupt Controller (NVIC)

The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low

interrupt latency and efficient processing of late arriving interrupts.

7.8.1 Features

• Controls system exceptions and peripheral interrupts.

• In the LPC178x/7x, the NVIC supports 41 vectored interrupts.

• 32 programmable interrupt priority levels, with hardware priority level masking.

• Relocatable vector table.

• Non-Maskable Interrupt (NMI).

• Software interrupt generation.

7.8.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

Any pin on port 0 and port 2 regardless of the selected function can be programmed to

generate an interrupt on a rising edge, a falling edge, or both.

7.9 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals.

Peripherals should be connected to the appropriate pins prior to being activated and prior

to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or

no resistor enabled.

7.10 External memory controller

Remark: Supported memory size and type and EMC bus width vary for different parts

(see Table 2). The EMC pin configuration for each part is shown in Table 7.

LPC178X Datasheet(PDF) 44 Page - NXP Semiconductors