LPC178X datasheet(93/117 Pages) NXP

93 / 117 page

LPC178X_7X

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Objective data sheet

Rev. 2 — 27 May 2011

93 of 117

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

11.10 Ethernet

Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76.

[1]

Output drivers can drive a load

 25 pF accommodating over 12 inch of PCB trace and the input

capacitance of the receiving device.

[2]

Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or

output level.

Fig 27. Differential data-to-EOP transition skew and EOP width

002aab561

tPERIOD

differential

data lines

crossover point

source EOP width: tFEOPT

receiver EOP width: tEOPR1, tEOPR2

crossover point

extended

differential data to

SE0/EOP skew

× tPERIOD + tFDEOP

Table 26.

Dynamic characteristics: Ethernet

Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.

Symbol Parameter

Conditions

Min

Max

Unit

RMII mode

fclk

clock frequency

for ENET_RX_CLK

[1]

-50

MHz

dclk

clock duty cycle

[1]

tsu

set-up time

for ENET_TXDn, ENET_TX_EN,

ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

hold time

for ENET_TXDn, ENET_TX_EN,

ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

MII mode

fclk

clock frequency

for ENET_TX_CLK

[1]

MHz

dclk

clock duty cycle

[1]

tsu

set-up time

for ENET_TXDn, ENET_TX_EN,

ENET_TX_ER

[1][2]

hold time

for ENET_TXDn, ENET_TX_EN,

ENET_TX_ER

[1][2]

fclk

clock frequency

for ENET_RX_CLK

[1]

MHz

dclk

clock duty cycle

[1]

tsu

set-up time

for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

hold time

for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

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