LPC178X datasheet(91/117 Pages) NXP

91 / 117 page

LPC178X_7X

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Objective data sheet

Rev. 2 — 27 May 2011

91 of 117

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

11.8 I2S-bus interface

[1]

CCLK = 100 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK / 4. I2S clock cycle time Tcy(clk) =

1600 ns, corresponds to the SCK signal in the I2S-bus specification.

Table 24.

Dynamic characteristics: I2S-bus interface pins

Tamb = 40 C to 85 C, VDD(REG)(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.

Symbol

Parameter

Conditions

Min

Max

Unit

common to input and output

rise time

[1]

-6.7

fall time

[1]

-8.0

tWH

pulse width HIGH

on pins I2S_TX_SCK and

I2S_RX_SCK

[1]

tWL

pulse width LOW

on pins I2S_TX_SCK and

I2S_RX_SCK

[1]

-25

output

tv(Q)

data output valid time

on pin I2S_TX_SDA;

[1]

-6

input

tsu(D)

data input set-up time

on pin I2S_RX_SDA

[1]

th(D)

data input hold time

on pin I2S_RX_SDA

[1]

Fig 25. I2S-bus timing (transmit)

002aag202

I2S_TX_SCK

I2S_TX_SDA

I2S_TX_WS

Tcy(clk)

tWH

tWL

tv(Q)

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