L3GD20TR datasheet(12/44 Pages) STMICROELECTRONICS

12 / 44 page

Mechanical and electrical specifications

L3GD20

12/44

Doc ID 022116 Rev 1

2.4.2

I2C - Inter IC control interface

Subject to general operating conditions for Vdd and Top.

Figure 4.

I2C slave timing diagram (b)

Table 7.

I2C slave timing values (TBC)

Symbol

Parameter

I2C standard mode(1)

I2C fast mode (1)

Unit

Min

Max

Min

Max

f(SCL)

SCL clock frequency

100

400

kHz

tw(SCLL)

SCL clock low time

4.7

1.3

µs

tw(SCLH)

SCL clock high time

4.0

0.6

tsu(SDA)

SDA setup time

250

100

th(SDA)

SDA data hold time

3.45

0.9

µs

tr(SDA) tr(SCL)

SDA and SCL rise time

1000

20 + 0.1Cb

(2)

300

tf(SDA) tf(SCL)

SDA and SCL fall time

300

20 + 0.1Cb

(2)

300

th(ST)

START condition hold time

0.6

µs

tsu(SR)

Repeated START condition

setup time

4.7

0.6

tsu(SP)

STOP condition setup time

0.6

tw(SP:SR)

Bus free time between STOP

and START condition

4.7

1.3

Data based on standard I2C protocol requirement; not tested in production.

Cb = total capacitance of one bus line, in pF.

Measurement points are at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

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