L3GD20TR datasheet(39/44 Pages) STMICROELECTRONICS

39 / 44 page

L3GD20

Doc ID 022116 Rev 1

39/44

Reading at this address clears INT1_SRC IA bit (and eventually the interrupt signal on the

INT1 pin) and allows the refresh of data in the INT1_SRC register if the latched option was

chosen.

7.17

INT1_THS_XH (32h)

7.18

INT1_THS_XL (33h)

7.19

INT1_THS_YH (34h)

7.20

INT1_THS_YL (35h)

Table 47.

INT1_THS_XH register

THSX14

THSX13

THSX12

THSX11

THSX10

THSX9

THSX8

Table 48.

INT1_THS_XH description

THSX14 - THSX9

Interrupt threshold. Default value: 0000 0000

Table 49.

INT1_THS_XL register

THSX7

THSX6

THSX5

THSX4

THSX3

THSX2

THSX1

THSX0

Table 50.

INT1_THS_XL description

THSX7 - THSX0

Interrupt threshold. Default value: 0000 0000

Table 51.

INT1_THS_YH register

THSY14

THSY13

THSY12

THSY11

THSY10

THSY9

THSY8

Table 52.

INT1_THS_YH description

THSY14 - THSY9

Interrupt threshold. Default value: 0000 0000

Table 53.

INT1_THS_YL register

THSR7

THSY6

THSY5

THSY4

THSY3

THSY2

THSY1

THSY0

Table 54.

INT1_THS_YL description

THSY7 - THSY0

Interrupt threshold. Default value: 0000 0000

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