L3GD20TR datasheet(31/44 Pages) STMICROELECTRONICS

31 / 44 page

L3GD20

Doc ID 022116 Rev 1

31/44

The device contains a set of registers which are used to control its behavior and to retrieve

angular rate data. The register address, consisting of 7 bits, is used to identify them and to

write the data through the serial interface.

7.1

WHO_AM_I (0Fh)

Device identification register.

7.2

CTRL_REG1 (20h)

DR<1:0> is used for ODR selection. BW <1:0> is used for Bandwidth selection.

In the

Table 20 all frequencies resulting in combinations of DR / BW bits are reported.

Table 17.

WHO_AM_I register

101

Table 18.

CTRL_REG1 register

DR1

DR0

BW1

BW0

Zen

Xen

Yen

Table 19.

CTRL_REG1 description

DR1-DR0

Output data rate selection. Refer to

Table 20

BW1-BW0

Bandwidth selection. Refer to

Table 20

Power-down mode enable. Default value: 0

(0: power-down mode, 1: normal mode or sleep mode)

Zen

Z axis enable. Default value: 1

(0: Z axis disabled; 1: Z axis enabled)

Yen

Y axis enable. Default value: 1

(0: Y axis disabled; 1: Y axis enabled)

Xen

X axis enable. Default value: 1

(0: X axis disabled; 1: X axis enabled)

Table 20.

DR and BW configuration setting

DR <1:0>

BW <1:0>

ODR [Hz]

Cut-Off

12.5

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