IC-NQL datasheet(18/24 Pages) ICHAUS

18 / 24 page

iC-NQL

13-bit Sin/D CONVERTER WITH SSI INTERFACE

Rev D2, Page 18/24

TEST FUNCTIONS

TMODE

Adr 0x06, Bit 3:1

Code

Signal at Z

Description

0x00

no test mode

0x01

A xor B

Output A EXOR B

0x02

ENCLK

iC-Haus device test

0x03

NLOCK

iC-Haus device test

0x04

CLK

iC-Haus device test

0x05

DIVC

iC-Haus device test

0x06

PZERO - NZERO

iC-Haus device test

0x07

iC-Haus device test

Condition

CFGABZ = 0x00

Table 29: Test Mode

TMA

Adr 0x06, Bit 0

Code

Pin A

Pin B

Pin SDA

Pin SCL

0x00

SDA

SCL

0x01

COS+

COS-

SIN+

SIN-

Notes

To permit the veriﬁcation of GAIN and OFFSET

settings, the input ampliﬁer outputs are available at

the pins. To operate the converter a signal of 4 Vpp

is the ideal here and should not be exceeded. Pin

loads above 1 MΩ are adviceable for accurate

measurements.

Table 30: Analog Test Mode

SDA: Sin+

A: COS+

5 V

X/Y

0 V

1 V/Div vert. 1 V/Div hor.

Y/T

1 V/Div vert.

Figure 14: Calibrated signals with TMA mode.

Parameter GAIN ideally adjusts the signal levels to ca.

4 Vpp and should not be touched afterwards.

Both scope display modes are feasible for OFFS (pos-

itive values) or RATIO adjustments; regarding the ad-

justment of PHASE the X/Y mode may be preferred.

For OFFS adjustment towards negative values the test

signals COS- (pin B) and SIN- (pin SCL) are relevant.

IC-NQL Datasheet(PDF) 18 Page - IC-Haus GmbH

IC-NQL Datasheet(HTML) 18 Page - IC-Haus GmbH

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL