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LPC4350 Datasheet(PDF) 116 Page - NXP Semiconductors |
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LPC4350 Datasheet(HTML) 116 Page - NXP Semiconductors |
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116 / 149 page  LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Objective data sheet Rev. 3.1 — 5 January 2012 116 of 149 NXP Semiconductors LPC4350/30/20/10 32-bit ARM Cortex-M4/M0 microcontroller For the programmable EMC_CLK[3:0] clock delays CLKn_DELAY, see Table 20 . Remark: For SDRAM operation, set CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY in the EMCDELAYCLK register. Fig 31. SDRAM timing 002aag703 Tcy(clk) EMC_CLKn delay = 0 EMC_CLKn delay > 0 EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_CKEOUTn, EMC_A[22:0], EMC_DQMOUTn th(Q) th(Q) - td th(D) tsu(D) th(D) tsu(D) EMC_D[31:0] write EMC_D[31:0] read; delay = 0 EMC_D[31:0] read; delay > 0 th(x) - td td(xV) - td td(QV) - td td(QV) th(x) td(xV) EMC_CLKn delay td; programmable CLKn_DELAY |
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