LPC4350 datasheet(119/149 Pages) PHILIPS

119 / 149 page

LPC4350_30_20_10

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Objective data sheet

Rev. 3.1 — 5 January 2012

119 of 149

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

[1]

Output drivers can drive a load

 25 pF accommodating over 12 inch of PCB trace and the input

capacitance of the receiving device.

[2]

Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or

output level.

tsu

set-up time

for ENET_TXDn, ENET_TX_EN,

ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

hold time

for ENET_TXDn, ENET_TX_EN,

ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

MII mode

fclk

clock frequency

for ENET_TX_CLK

[1]

MHz



clk

clock duty cycle

[1]

tsu

set-up time

for ENET_TXDn, ENET_TX_EN,

ENET_TX_ER

[1][2]

hold time

for ENET_TXDn, ENET_TX_EN,

ENET_TX_ER

[1][2]

fclk

clock frequency

for ENET_RX_CLK

[1]

MHz



clk

clock duty cycle

[1]

tsu

set-up time

for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

hold time

for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV

[1][2]

Fig 33. Ethernet timing

Table 23.

Dynamic characteristics: Ethernet

Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Values guaranteed by

design.

Symbol Parameter

Conditions

Min

Max

Unit

002aag210

tsu

ENET_RX_CLK

ENET_TX_CLK

ENET_RXD[n]

ENET_RX_DV

ENET_RX_ER

ENET_TXD[n]

ENET_TX_EN

ENET_TX_ER

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